Lines Matching defs:val
108 #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val))
109 #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val))
115 #define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val))
293 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg)
295 writel(val, pcie->base + reg);
305 u32 val;
308 val = advk_readl(pcie, CFG_REG);
309 ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
653 static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u32 *val)
688 if (val)
689 *val = advk_readl(pcie, PIO_RD_DATA);
699 if (allow_crs && val) {
712 *val = CFG_RD_CRS_VAL;
797 u32 val = le32_to_cpu(cfgspace[PCI_INTERRUPT_LINE / 4]);
799 val &= ~(PCI_BRIDGE_CTL_SERR << 16);
801 val |= PCI_BRIDGE_CTL_SERR << 16;
803 val |= PCI_BRIDGE_CTL_BUS_RESET << 16;
805 val &= ~(PCI_BRIDGE_CTL_BUS_RESET << 16);
806 *value = val;
833 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG);
835 val &= ~PCIE_ISR0_ERR_MASK;
837 val |= PCIE_ISR0_ERR_MASK;
838 advk_writel(pcie, val, PCIE_ISR0_MASK_REG);
841 u32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG);
843 val |= HOT_RESET_GEN;
845 val &= ~HOT_RESET_GEN;
846 advk_writel(pcie, val, PCIE_CORE_CTRL1_REG);
871 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg);
877 val |= PCI_EXP_LNKCAP_DLLLARC;
878 *value = val;
884 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) &
887 val |= (PCI_EXP_LNKSTA_LT << 16);
889 val |= (PCI_EXP_LNKSTA_DLLLA << 16);
890 *value = val;
1141 int where, int size, u32 *val)
1154 size, val);
1198 ret = advk_pcie_check_pio_status(pcie, allow_crs, val);
1205 *val = (*val >> (8 * (where & 3))) & 0xff;
1207 *val = (*val >> (8 * (where & 3))) & 0xffff;
1217 *val = CFG_RD_CRS_VAL;
1222 *val = 0xffffffff;
1227 int where, int size, u32 val)
1241 size, val);
1265 reg = val << (8 * offset);
1934 u32 val;
1944 val = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
1945 val &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
1946 advk_writel(pcie, val, PCIE_CORE_CMD_STATUS_REG);
1949 val = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
1950 val &= ~PCIE_CORE_CTRL2_MSI_ENABLE;
1951 advk_writel(pcie, val, PCIE_CORE_CTRL2_REG);
1982 val = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
1983 val &= ~LINK_TRAINING_EN;
1984 advk_writel(pcie, val, PCIE_CORE_CTRL0_REG);