Lines Matching refs:pcie
25 #include "pcie-mobiveil.h"
50 struct mobiveil_pcie *pcie = bus->sysdata;
51 struct mobiveil_root_port *rp = &pcie->rp;
59 return pcie->csr_axi_slave_base + where;
71 mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
85 struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc);
86 struct device *dev = &pcie->pdev->dev;
87 struct mobiveil_root_port *rp = &pcie->rp;
102 val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
103 mask = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
108 shifted_status = mobiveil_csr_readl(pcie,
122 mobiveil_csr_writel(pcie,
127 shifted_status = mobiveil_csr_readl(pcie,
135 msi_status = readl_relaxed(pcie->apb_csr_base + MSI_STATUS_OFFSET);
139 msi_data = readl_relaxed(pcie->apb_csr_base + MSI_DATA_OFFSET);
147 msi_addr_lo = readl_relaxed(pcie->apb_csr_base +
149 msi_addr_hi = readl_relaxed(pcie->apb_csr_base +
156 msi_status = readl_relaxed(pcie->apb_csr_base +
161 mobiveil_csr_writel(pcie, intr_status, PAB_INTP_AMBA_MISC_STAT);
165 static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
167 struct device *dev = &pcie->pdev->dev;
168 struct platform_device *pdev = pcie->pdev;
170 struct mobiveil_root_port *rp = &pcie->rp;
184 pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
185 if (IS_ERR(pcie->csr_axi_slave_base))
186 return PTR_ERR(pcie->csr_axi_slave_base);
187 pcie->pcie_reg_base = res->start;
190 if (of_property_read_u32(node, "apio-wins", &pcie->apio_wins))
191 pcie->apio_wins = MAX_PIO_WINDOWS;
193 if (of_property_read_u32(node, "ppio-wins", &pcie->ppio_wins))
194 pcie->ppio_wins = MAX_PIO_WINDOWS;
199 static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)
201 phys_addr_t msg_addr = pcie->pcie_reg_base;
202 struct mobiveil_msi *msi = &pcie->rp.msi;
208 pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
210 pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
211 writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET);
212 writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);
215 int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit)
217 struct mobiveil_root_port *rp = &pcie->rp;
222 pcie->ib_wins_configured = 0;
223 pcie->ob_wins_configured = 0;
227 value = mobiveil_csr_readl(pcie, PCI_PRIMARY_BUS);
230 mobiveil_csr_writel(pcie, value, PCI_PRIMARY_BUS);
237 value = mobiveil_csr_readl(pcie, PCI_COMMAND);
239 mobiveil_csr_writel(pcie, value, PCI_COMMAND);
245 pab_ctrl = mobiveil_csr_readl(pcie, PAB_CTRL);
247 mobiveil_csr_writel(pcie, pab_ctrl, PAB_CTRL);
253 value = mobiveil_csr_readl(pcie, PAB_AXI_PIO_CTRL);
255 mobiveil_csr_writel(pcie, value, PAB_AXI_PIO_CTRL);
258 value = mobiveil_csr_readl(pcie, PAB_PEX_PIO_CTRL);
260 mobiveil_csr_writel(pcie, value, PAB_PEX_PIO_CTRL);
270 program_ob_windows(pcie, WIN_NUM_0, rp->ob_io_res->start, 0,
274 program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
286 program_ob_windows(pcie, pcie->ob_wins_configured,
293 value = mobiveil_csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS);
296 mobiveil_csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);
303 struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data);
308 rp = &pcie->rp;
311 shifted_val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
313 mobiveil_csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
319 struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data);
324 rp = &pcie->rp;
327 shifted_val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
329 mobiveil_csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
370 struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data);
371 phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int));
377 dev_dbg(&pcie->pdev->dev, "msi#%d address_hi %#x address_lo %#x\n",
397 struct mobiveil_pcie *pcie = domain->host_data;
398 struct mobiveil_msi *msi = &pcie->rp.msi;
424 struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d);
425 struct mobiveil_msi *msi = &pcie->rp.msi;
430 dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n",
442 static int mobiveil_allocate_msi_domains(struct mobiveil_pcie *pcie)
444 struct device *dev = &pcie->pdev->dev;
446 struct mobiveil_msi *msi = &pcie->rp.msi;
450 &msi_domain_ops, pcie);
468 static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie)
470 struct device *dev = &pcie->pdev->dev;
472 struct mobiveil_root_port *rp = &pcie->rp;
476 &intx_domain_ops, pcie);
486 return mobiveil_allocate_msi_domains(pcie);
489 static int mobiveil_pcie_integrated_interrupt_init(struct mobiveil_pcie *pcie)
491 struct platform_device *pdev = pcie->pdev;
493 struct mobiveil_root_port *rp = &pcie->rp;
499 pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res);
500 if (IS_ERR(pcie->apb_csr_base))
501 return PTR_ERR(pcie->apb_csr_base);
504 mobiveil_pcie_enable_msi(pcie);
511 ret = mobiveil_pcie_init_irq_domain(pcie);
517 irq_set_chained_handler_and_data(rp->irq, mobiveil_pcie_isr, pcie);
520 mobiveil_csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),
527 static int mobiveil_pcie_interrupt_init(struct mobiveil_pcie *pcie)
529 struct mobiveil_root_port *rp = &pcie->rp;
532 return rp->ops->interrupt_init(pcie);
534 return mobiveil_pcie_integrated_interrupt_init(pcie);
537 static bool mobiveil_pcie_is_bridge(struct mobiveil_pcie *pcie)
541 header_type = mobiveil_csr_readb(pcie, PCI_HEADER_TYPE);
547 int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie)
549 struct mobiveil_root_port *rp = &pcie->rp;
551 struct device *dev = &pcie->pdev->dev;
554 ret = mobiveil_pcie_parse_dt(pcie);
560 if (!mobiveil_pcie_is_bridge(pcie))
567 ret = mobiveil_host_init(pcie, false);
573 ret = mobiveil_pcie_interrupt_init(pcie);
580 bridge->sysdata = pcie;
583 ret = mobiveil_bringup_link(pcie);