Lines Matching refs:val
97 static void visconti_ulreg_writel(struct visconti_pcie *pcie, u32 val, u32 reg)
99 writel_relaxed(val, pcie->ulreg_base + reg);
108 static void visconti_smu_writel(struct visconti_pcie *pcie, u32 val, u32 reg)
110 writel_relaxed(val, pcie->smu_base + reg);
114 static void visconti_mpu_writel(struct visconti_pcie *pcie, u32 val, u32 reg)
116 writel_relaxed(val, pcie->mpu_base + reg);
128 u32 val = readl_relaxed(addr + PCIE_UL_REG_V_PHY_ST_02);
130 return !!(val & PCIE_UL_S_L0);
137 u32 val;
144 val, (val & PCIE_UL_S_L0),
153 val = visconti_mpu_readl(pcie, PCIE_MPU_REG_MP_EN);
154 visconti_mpu_writel(pcie, val & ~MPU_MP_EN_DISABLE,
164 u32 val;
166 val = visconti_ulreg_readl(pcie, PCIE_UL_REG_V_SII_GEN_CTRL_01);
167 val &= ~PCIE_UL_APP_LTSSM_ENABLE;
168 visconti_ulreg_writel(pcie, val, PCIE_UL_REG_V_SII_GEN_CTRL_01);
170 val = visconti_mpu_readl(pcie, PCIE_MPU_REG_MP_EN);
171 visconti_mpu_writel(pcie, val | MPU_MP_EN_DISABLE, PCIE_MPU_REG_MP_EN);
199 u32 val;
211 val = PCIE_UL_REG_S_PERSTN_CTRL_INIT;
212 visconti_ulreg_writel(pcie, val, PCIE_UL_REG_S_PERSTN_CTRL);
215 val |= PCIE_UL_PERSTN_OUT;
216 visconti_ulreg_writel(pcie, val, PCIE_UL_REG_S_PERSTN_CTRL);
223 err = readl_relaxed_poll_timeout(addr, val,
224 (val & PCIE_UL_PHY0_SRAM_INIT_DONE),
233 return readl_relaxed_poll_timeout(addr, val,
234 (val & PCIE_UL_CORE_RST_N_MON), 100,