Lines Matching refs:pcie
24 #include "pcie-designware.h"
97 static void visconti_ulreg_writel(struct visconti_pcie *pcie, u32 val, u32 reg)
99 writel_relaxed(val, pcie->ulreg_base + reg);
102 static u32 visconti_ulreg_readl(struct visconti_pcie *pcie, u32 reg)
104 return readl_relaxed(pcie->ulreg_base + reg);
108 static void visconti_smu_writel(struct visconti_pcie *pcie, u32 val, u32 reg)
110 writel_relaxed(val, pcie->smu_base + reg);
114 static void visconti_mpu_writel(struct visconti_pcie *pcie, u32 val, u32 reg)
116 writel_relaxed(val, pcie->mpu_base + reg);
119 static u32 visconti_mpu_readl(struct visconti_pcie *pcie, u32 reg)
121 return readl_relaxed(pcie->mpu_base + reg);
126 struct visconti_pcie *pcie = dev_get_drvdata(pci->dev);
127 void __iomem *addr = pcie->ulreg_base;
135 struct visconti_pcie *pcie = dev_get_drvdata(pci->dev);
136 void __iomem *addr = pcie->ulreg_base;
140 visconti_ulreg_writel(pcie, PCIE_UL_APP_LTSSM_ENABLE,
149 visconti_ulreg_writel(pcie, PCIE_UL_S_INT_EVENT_MASK1_ALL,
153 val = visconti_mpu_readl(pcie, PCIE_MPU_REG_MP_EN);
154 visconti_mpu_writel(pcie, val & ~MPU_MP_EN_DISABLE,
163 struct visconti_pcie *pcie = dev_get_drvdata(pci->dev);
166 val = visconti_ulreg_readl(pcie, PCIE_UL_REG_V_SII_GEN_CTRL_01);
168 visconti_ulreg_writel(pcie, val, PCIE_UL_REG_V_SII_GEN_CTRL_01);
170 val = visconti_mpu_readl(pcie, PCIE_MPU_REG_MP_EN);
171 visconti_mpu_writel(pcie, val | MPU_MP_EN_DISABLE, PCIE_MPU_REG_MP_EN);
196 struct visconti_pcie *pcie = dev_get_drvdata(pci->dev);
201 visconti_smu_writel(pcie,
206 visconti_smu_writel(pcie, PISMU_RSOFF_PCIE_ULREG_RST_N,
208 visconti_ulreg_writel(pcie, PCIE_UL_REG_S_PCIE_MODE_RC,
212 visconti_ulreg_writel(pcie, val, PCIE_UL_REG_S_PERSTN_CTRL);
216 visconti_ulreg_writel(pcie, val, PCIE_UL_REG_S_PERSTN_CTRL);
219 visconti_smu_writel(pcie, PISMU_RSOFF_PCIE_PWR_UP_RST_N,
222 addr = pcie->ulreg_base + PCIE_UL_REG_S_PHY_INIT_03;
229 visconti_ulreg_writel(pcie, PCIE_UL_PHY0_SRAM_EXT_LD_DONE,
232 addr = pcie->ulreg_base + PCIE_UL_REG_S_SIG_MON;
243 struct visconti_pcie *pcie)
247 pcie->ulreg_base = devm_platform_ioremap_resource_byname(pdev, "ulreg");
248 if (IS_ERR(pcie->ulreg_base))
249 return PTR_ERR(pcie->ulreg_base);
251 pcie->smu_base = devm_platform_ioremap_resource_byname(pdev, "smu");
252 if (IS_ERR(pcie->smu_base))
253 return PTR_ERR(pcie->smu_base);
255 pcie->mpu_base = devm_platform_ioremap_resource_byname(pdev, "mpu");
256 if (IS_ERR(pcie->mpu_base))
257 return PTR_ERR(pcie->mpu_base);
259 pcie->refclk = devm_clk_get(dev, "ref");
260 if (IS_ERR(pcie->refclk))
261 return dev_err_probe(dev, PTR_ERR(pcie->refclk),
264 pcie->coreclk = devm_clk_get(dev, "core");
265 if (IS_ERR(pcie->coreclk))
266 return dev_err_probe(dev, PTR_ERR(pcie->coreclk),
269 pcie->auxclk = devm_clk_get(dev, "aux");
270 if (IS_ERR(pcie->auxclk))
271 return dev_err_probe(dev, PTR_ERR(pcie->auxclk),
277 static int visconti_add_pcie_port(struct visconti_pcie *pcie,
280 struct dw_pcie *pci = &pcie->pci;
295 struct visconti_pcie *pcie;
299 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
300 if (!pcie)
303 pci = &pcie->pci;
307 ret = visconti_get_resources(pdev, pcie);
311 platform_set_drvdata(pdev, pcie);
313 return visconti_add_pcie_port(pcie, pdev);
317 { .compatible = "toshiba,visconti-pcie" },
324 .name = "visconti-pcie",