Lines Matching refs:val
78 u32 val;
80 val = readl(pcie->base + PCL_APP_READY_CTRL);
82 val |= PCL_APP_LTSSM_ENABLE;
84 val &= ~PCL_APP_LTSSM_ENABLE;
85 writel(val, pcie->base + PCL_APP_READY_CTRL);
90 u32 val;
93 val = readl(pcie->base + PCL_MODE);
94 val |= PCL_MODE_REGEN;
95 val &= ~PCL_MODE_REGVAL;
96 writel(val, pcie->base + PCL_MODE);
99 val = readl(pcie->base + PCL_APP_PM0);
100 val |= PCL_SYS_AUX_PWR_DET;
101 writel(val, pcie->base + PCL_APP_PM0);
104 val = readl(pcie->base + PCL_PINCTRL0);
105 val &= ~(PCL_PERST_NOE_REGVAL | PCL_PERST_OUT_REGVAL
107 val |= PCL_PERST_NOE_REGEN | PCL_PERST_OUT_REGEN
109 writel(val, pcie->base + PCL_PINCTRL0);
116 val = readl(pcie->base + PCL_PINCTRL0);
117 val |= PCL_PERST_OUT_REGVAL | PCL_PERST_OUT_REGEN;
118 writel(val, pcie->base + PCL_PINCTRL0);
141 u32 val, mask;
143 val = readl(pcie->base + PCL_STATUS_LINK);
146 return (val & mask) == mask;
178 u32 val;
182 val = readl(pcie->base + PCL_RCV_INTX);
183 val |= BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);
184 writel(val, pcie->base + PCL_RCV_INTX);
195 u32 val;
199 val = readl(pcie->base + PCL_RCV_INTX);
200 val &= ~BIT(irqd_to_hwirq(d) + PCL_RCV_INTX_MASK_SHIFT);
201 writel(val, pcie->base + PCL_RCV_INTX);
233 u32 val, bit;
236 val = readl(pcie->base + PCL_RCV_INT);
238 if (val & PCL_CFG_BW_MGT_STATUS)
240 if (val & PCL_CFG_LINK_AUTO_BW_STATUS)
242 if (val & PCL_CFG_AER_RC_ERR_MSI_STATUS)
244 if (val & PCL_CFG_PME_MSI_STATUS)
247 writel(val, pcie->base + PCL_RCV_INT);
252 val = readl(pcie->base + PCL_RCV_INTX);
253 reg = FIELD_GET(PCL_RCV_INTX_ALL_STATUS, val);