Lines Matching refs:val

93 	u32 val;
95 val = readl(priv->base + PCL_APP_READY_CTRL);
97 val |= PCL_APP_LTSSM_ENABLE;
99 val &= ~PCL_APP_LTSSM_ENABLE;
100 writel(val, priv->base + PCL_APP_READY_CTRL);
106 u32 val;
108 val = readl(priv->base + PCL_RSTCTRL2);
110 val |= PCL_RSTCTRL_PHY_RESET;
112 val &= ~PCL_RSTCTRL_PHY_RESET;
113 writel(val, priv->base + PCL_RSTCTRL2);
118 u32 val;
121 val = readl(priv->base + PCL_MODE);
122 val |= PCL_MODE_REGEN | PCL_MODE_REGVAL;
123 writel(val, priv->base + PCL_MODE);
126 val = readl(priv->base + PCL_APP_CLK_CTRL);
127 val &= ~PCL_APP_CLK_REQ;
128 writel(val, priv->base + PCL_APP_CLK_CTRL);
131 val = readl(priv->base + PCL_RSTCTRL0);
132 val |= PCL_RSTCTRL_AXI_REG | PCL_RSTCTRL_AXI_SLAVE
134 writel(val, priv->base + PCL_RSTCTRL0);
143 u32 val;
146 val = readl(priv->base + PCL_MODE);
147 val |= PCL_MODE_REGEN | PCL_MODE_REGVAL;
148 writel(val, priv->base + PCL_MODE);
151 val = readl(priv->base + PCL_APP_PM0);
152 val |= PCL_SYS_AUX_PWR_DET;
153 writel(val, priv->base + PCL_APP_PM0);
156 val = readl(priv->base + PCL_PINCTRL0);
157 val &= ~(PCL_PERST_NOE_REGVAL | PCL_PERST_OUT_REGVAL
159 val |= PCL_PERST_NOE_REGEN | PCL_PERST_OUT_REGEN
161 writel(val, priv->base + PCL_PINCTRL0);
168 val = readl(priv->base + PCL_PINCTRL0);
169 val |= PCL_PERST_OUT_REGVAL | PCL_PERST_OUT_REGEN;
170 writel(val, priv->base + PCL_PINCTRL0);
219 u32 val;
227 val = readl(priv->base + PCL_APP_INTX);
228 val |= PCL_APP_INTX_SYS_INT;
229 writel(val, priv->base + PCL_APP_INTX);
234 val &= ~PCL_APP_INTX_SYS_INT;
235 writel(val, priv->base + PCL_APP_INTX);
245 u32 val;
247 val = FIELD_PREP(PCL_APP_VEN_MSI_TC_MASK, func_no)
249 writel(val, priv->base + PCL_APP_MSI0);
251 val = readl(priv->base + PCL_APP_MSI1);
252 val |= PCL_APP_MSI_REQ;
253 writel(val, priv->base + PCL_APP_MSI1);