Lines Matching refs:pcie
35 #include "pcie-designware.h"
300 static inline void appl_writel(struct tegra_pcie_dw *pcie, const u32 value,
303 writel_relaxed(value, pcie->appl_base + reg);
306 static inline u32 appl_readl(struct tegra_pcie_dw *pcie, const u32 reg)
308 return readl_relaxed(pcie->appl_base + reg);
315 static void tegra_pcie_icc_set(struct tegra_pcie_dw *pcie)
317 struct dw_pcie *pci = &pcie->pci;
320 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA);
327 if (icc_set_bw(pcie->icc_path, MBps_to_icc(val), 0))
328 dev_err(pcie->dev, "can't set bw[%u]\n", val);
333 clk_set_rate(pcie->core_clk, pcie_gen_freq[speed]);
339 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
348 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA);
351 if (pcie->init_link_width > current_link_width) {
353 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
357 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base +
360 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
363 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base +
371 struct tegra_pcie_dw *pcie = arg;
372 struct dw_pcie *pci = &pcie->pci;
377 status_l0 = appl_readl(pcie, APPL_INTR_STATUS_L0);
379 status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0);
380 appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_0_0);
381 if (!pcie->of_data->has_sbr_reset_fix &&
384 val = appl_readl(pcie, APPL_CAR_RESET_OVRD);
386 appl_writel(pcie, val, APPL_CAR_RESET_OVRD);
388 val = appl_readl(pcie, APPL_CAR_RESET_OVRD);
390 appl_writel(pcie, val, APPL_CAR_RESET_OVRD);
399 status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_8_0);
401 appl_writel(pcie,
407 val_w = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
410 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base +
413 appl_writel(pcie,
417 val_w = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
425 status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_18);
447 static void pex_ep_event_hot_rst_done(struct tegra_pcie_dw *pcie)
451 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0);
452 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0);
453 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1);
454 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2);
455 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3);
456 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6);
457 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7);
458 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0);
459 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9);
460 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10);
461 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11);
462 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13);
463 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14);
464 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15);
465 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17);
466 appl_writel(pcie, 0xFFFFFFFF, APPL_MSI_CTRL_2);
468 val = appl_readl(pcie, APPL_CTRL);
470 appl_writel(pcie, val, APPL_CTRL);
475 struct tegra_pcie_dw *pcie = arg;
476 struct dw_pcie_ep *ep = &pcie->pci.ep;
477 struct dw_pcie *pci = &pcie->pci;
480 if (test_and_clear_bit(0, &pcie->link_status))
483 tegra_pcie_icc_set(pcie);
485 if (pcie->of_data->has_ltr_req_fix)
489 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub);
501 appl_writel(pcie, val, APPL_LTR_MSG_1);
504 val = appl_readl(pcie, APPL_LTR_MSG_2);
506 appl_writel(pcie, val, APPL_LTR_MSG_2);
510 val = appl_readl(pcie, APPL_LTR_MSG_2);
518 dev_err(pcie->dev, "Failed to send LTR message\n");
526 struct tegra_pcie_dw *pcie = arg;
530 status_l0 = appl_readl(pcie, APPL_INTR_STATUS_L0);
532 status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0);
533 appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_0_0);
536 pex_ep_event_hot_rst_done(pcie);
539 link_status = appl_readl(pcie, APPL_LINK_STATUS);
541 dev_dbg(pcie->dev, "Link is up with Host\n");
542 set_bit(0, &pcie->link_status);
551 status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_15);
552 appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_15);
561 dev_warn(pcie->dev, "Random interrupt (STATUS = 0x%08X)\n",
563 appl_writel(pcie, status_l0, APPL_INTR_STATUS_L0);
574 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
582 if (!pcie->of_data->has_msix_doorbell_access_fix &&
596 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
604 if (!pcie->of_data->has_msix_doorbell_access_fix &&
618 static void disable_aspm_l11(struct tegra_pcie_dw *pcie)
622 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub);
624 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val);
627 static void disable_aspm_l12(struct tegra_pcie_dw *pcie)
631 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub);
633 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val);
636 static inline u32 event_counter_prog(struct tegra_pcie_dw *pcie, u32 event)
640 val = dw_pcie_readl_dbi(&pcie->pci, pcie->ras_des_cap +
646 dw_pcie_writel_dbi(&pcie->pci, pcie->ras_des_cap +
648 val = dw_pcie_readl_dbi(&pcie->pci, pcie->ras_des_cap +
656 struct tegra_pcie_dw *pcie = (struct tegra_pcie_dw *)
661 event_counter_prog(pcie, EVENT_COUNTER_EVENT_Tx_L0S));
664 event_counter_prog(pcie, EVENT_COUNTER_EVENT_Rx_L0S));
667 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1));
670 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1_1));
673 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1_2));
676 dw_pcie_writel_dbi(&pcie->pci, pcie->ras_des_cap +
683 dw_pcie_writel_dbi(&pcie->pci, pcie->ras_des_cap +
689 static void init_host_aspm(struct tegra_pcie_dw *pcie)
691 struct dw_pcie *pci = &pcie->pci;
695 pcie->cfg_link_cap_l1sub = val + PCI_L1SS_CAP;
697 pcie->ras_des_cap = dw_pcie_find_ext_capability(&pcie->pci,
703 dw_pcie_writel_dbi(pci, pcie->ras_des_cap +
707 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub);
709 val |= (pcie->aspm_cmrt << 8);
710 val |= (pcie->aspm_pwr_on_t << 19);
711 dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val);
716 val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT);
721 static void init_debugfs(struct tegra_pcie_dw *pcie)
723 debugfs_create_devm_seqfile(pcie->dev, "aspm_state_cnt", pcie->debugfs,
727 static inline void disable_aspm_l12(struct tegra_pcie_dw *pcie) { return; }
728 static inline void disable_aspm_l11(struct tegra_pcie_dw *pcie) { return; }
729 static inline void init_host_aspm(struct tegra_pcie_dw *pcie) { return; }
730 static inline void init_debugfs(struct tegra_pcie_dw *pcie) { return; }
736 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
740 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
742 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
744 if (!pcie->of_data->has_sbr_reset_fix) {
745 val = appl_readl(pcie, APPL_INTR_EN_L1_0_0);
747 appl_writel(pcie, val, APPL_INTR_EN_L1_0_0);
750 if (pcie->enable_cdm_check) {
751 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
752 val |= pcie->of_data->cdm_chk_int_en_bit;
753 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
755 val = appl_readl(pcie, APPL_INTR_EN_L1_18);
758 appl_writel(pcie, val, APPL_INTR_EN_L1_18);
761 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base +
763 pcie->init_link_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, val_w);
765 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base +
768 dw_pcie_writew_dbi(&pcie->pci, pcie->pcie_cap_base + PCI_EXP_LNKCTL,
775 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
779 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
782 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
784 val = appl_readl(pcie, APPL_INTR_EN_L1_8_0);
790 appl_writel(pcie, val, APPL_INTR_EN_L1_8_0);
796 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
800 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
803 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
809 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
812 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0);
813 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0);
814 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1);
815 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2);
816 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3);
817 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6);
818 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7);
819 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0);
820 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9);
821 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10);
822 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11);
823 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13);
824 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14);
825 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15);
826 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17);
834 static void config_gen3_gen4_eq_presets(struct tegra_pcie_dw *pcie)
836 struct dw_pcie *pci = &pcie->pci;
840 for (i = 0; i < pcie->num_lanes; i++) {
878 val |= (pcie->of_data->gen4_preset_vec <<
891 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
897 if (!pcie->pcie_cap_base)
898 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
920 val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP);
922 val |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, pcie->num_lanes);
923 dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP, val);
926 if (pcie->enable_srns) {
927 val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
930 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA,
934 config_gen3_gen4_eq_presets(pcie);
936 init_host_aspm(pcie);
939 if (!pcie->supports_clkreq) {
940 disable_aspm_l11(pcie);
941 disable_aspm_l12(pcie);
944 if (!pcie->of_data->has_l1ss_exit_fix) {
950 if (pcie->update_fc_fixup) {
956 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
963 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
968 if (pcie->of_data->mode == DW_PCIE_EP_TYPE) {
969 enable_irq(pcie->pex_rst_irq);
975 val = appl_readl(pcie, APPL_PINMUX);
977 appl_writel(pcie, val, APPL_PINMUX);
982 val = appl_readl(pcie, APPL_CTRL);
984 appl_writel(pcie, val, APPL_CTRL);
987 val = appl_readl(pcie, APPL_PINMUX);
989 appl_writel(pcie, val, APPL_PINMUX);
1004 val = appl_readl(pcie, APPL_DEBUG);
1007 tmp = appl_readl(pcie, APPL_LINK_STATUS);
1017 val = appl_readl(pcie, APPL_CTRL);
1019 appl_writel(pcie, val, APPL_CTRL);
1021 reset_control_assert(pcie->core_rst);
1022 reset_control_deassert(pcie->core_rst);
1036 tegra_pcie_icc_set(pcie);
1045 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
1046 u32 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA);
1053 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
1055 disable_irq(pcie->pex_rst_irq);
1068 static void tegra_pcie_disable_phy(struct tegra_pcie_dw *pcie)
1070 unsigned int phy_count = pcie->phy_count;
1073 phy_power_off(pcie->phys[phy_count]);
1074 phy_exit(pcie->phys[phy_count]);
1078 static int tegra_pcie_enable_phy(struct tegra_pcie_dw *pcie)
1083 for (i = 0; i < pcie->phy_count; i++) {
1084 ret = phy_init(pcie->phys[i]);
1088 ret = phy_power_on(pcie->phys[i]);
1097 phy_power_off(pcie->phys[i]);
1099 phy_exit(pcie->phys[i]);
1105 static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
1107 struct platform_device *pdev = to_platform_device(pcie->dev);
1108 struct device_node *np = pcie->dev->of_node;
1111 pcie->dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
1112 if (!pcie->dbi_res) {
1113 dev_err(pcie->dev, "Failed to find \"dbi\" region\n");
1117 ret = of_property_read_u32(np, "nvidia,aspm-cmrt-us", &pcie->aspm_cmrt);
1119 dev_info(pcie->dev, "Failed to read ASPM T_cmrt: %d\n", ret);
1124 &pcie->aspm_pwr_on_t);
1126 dev_info(pcie->dev, "Failed to read ASPM Power On time: %d\n",
1130 &pcie->aspm_l0s_enter_lat);
1132 dev_info(pcie->dev,
1135 ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes);
1137 dev_err(pcie->dev, "Failed to read num-lanes: %d\n", ret);
1141 ret = of_property_read_u32_index(np, "nvidia,bpmp", 1, &pcie->cid);
1143 dev_err(pcie->dev, "Failed to read Controller-ID: %d\n", ret);
1149 dev_err(pcie->dev, "Failed to find PHY entries: %d\n",
1153 pcie->phy_count = ret;
1156 pcie->update_fc_fixup = true;
1159 if (pcie->of_data->version == TEGRA194_DWC_IP_VER) {
1160 if (pcie->of_data->mode == DW_PCIE_EP_TYPE)
1161 pcie->enable_ext_refclk = true;
1163 pcie->enable_ext_refclk =
1164 of_property_read_bool(pcie->dev->of_node,
1168 pcie->supports_clkreq =
1169 of_property_read_bool(pcie->dev->of_node, "supports-clkreq");
1171 pcie->enable_cdm_check =
1174 if (pcie->of_data->version == TEGRA234_DWC_IP_VER)
1175 pcie->enable_srns =
1178 if (pcie->of_data->mode == DW_PCIE_RC_TYPE)
1182 pcie->pex_rst_gpiod = devm_gpiod_get(pcie->dev, "reset", GPIOD_IN);
1183 if (IS_ERR(pcie->pex_rst_gpiod)) {
1184 int err = PTR_ERR(pcie->pex_rst_gpiod);
1190 dev_printk(level, pcie->dev,
1196 pcie->pex_refclk_sel_gpiod = devm_gpiod_get(pcie->dev,
1199 if (IS_ERR(pcie->pex_refclk_sel_gpiod)) {
1200 int err = PTR_ERR(pcie->pex_refclk_sel_gpiod);
1206 dev_printk(level, pcie->dev,
1209 pcie->pex_refclk_sel_gpiod = NULL;
1215 static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie,
1226 if (pcie->of_data->version == TEGRA194_DWC_IP_VER && pcie->cid == 5)
1233 req.controller_state.pcie_controller = pcie->cid;
1243 return tegra_bpmp_transfer(pcie->bpmp, &msg);
1246 static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie,
1258 req.ep_ctrlr_pll_init.ep_controller = pcie->cid;
1261 req.ep_ctrlr_pll_off.ep_controller = pcie->cid;
1271 return tegra_bpmp_transfer(pcie->bpmp, &msg);
1274 static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie)
1276 struct dw_pcie_rp *pp = &pcie->pci.pp;
1298 dev_err(pcie->dev, "Failed to find downstream devices\n");
1305 dev_err(pcie->dev,
1312 static int tegra_pcie_get_slot_regulators(struct tegra_pcie_dw *pcie)
1314 pcie->slot_ctl_3v3 = devm_regulator_get_optional(pcie->dev, "vpcie3v3");
1315 if (IS_ERR(pcie->slot_ctl_3v3)) {
1316 if (PTR_ERR(pcie->slot_ctl_3v3) != -ENODEV)
1317 return PTR_ERR(pcie->slot_ctl_3v3);
1319 pcie->slot_ctl_3v3 = NULL;
1322 pcie->slot_ctl_12v = devm_regulator_get_optional(pcie->dev, "vpcie12v");
1323 if (IS_ERR(pcie->slot_ctl_12v)) {
1324 if (PTR_ERR(pcie->slot_ctl_12v) != -ENODEV)
1325 return PTR_ERR(pcie->slot_ctl_12v);
1327 pcie->slot_ctl_12v = NULL;
1333 static int tegra_pcie_enable_slot_regulators(struct tegra_pcie_dw *pcie)
1337 if (pcie->slot_ctl_3v3) {
1338 ret = regulator_enable(pcie->slot_ctl_3v3);
1340 dev_err(pcie->dev,
1346 if (pcie->slot_ctl_12v) {
1347 ret = regulator_enable(pcie->slot_ctl_12v);
1349 dev_err(pcie->dev,
1360 if (pcie->slot_ctl_3v3 || pcie->slot_ctl_12v)
1366 if (pcie->slot_ctl_3v3)
1367 regulator_disable(pcie->slot_ctl_3v3);
1371 static void tegra_pcie_disable_slot_regulators(struct tegra_pcie_dw *pcie)
1373 if (pcie->slot_ctl_12v)
1374 regulator_disable(pcie->slot_ctl_12v);
1375 if (pcie->slot_ctl_3v3)
1376 regulator_disable(pcie->slot_ctl_3v3);
1379 static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
1385 ret = tegra_pcie_bpmp_set_ctrl_state(pcie, true);
1387 dev_err(pcie->dev,
1388 "Failed to enable controller %u: %d\n", pcie->cid, ret);
1392 if (pcie->enable_ext_refclk) {
1393 ret = tegra_pcie_bpmp_set_pll_state(pcie, true);
1395 dev_err(pcie->dev, "Failed to init UPHY: %d\n", ret);
1400 ret = tegra_pcie_enable_slot_regulators(pcie);
1404 ret = regulator_enable(pcie->pex_ctl_supply);
1406 dev_err(pcie->dev, "Failed to enable regulator: %d\n", ret);
1410 ret = clk_prepare_enable(pcie->core_clk);
1412 dev_err(pcie->dev, "Failed to enable core clock: %d\n", ret);
1416 ret = reset_control_deassert(pcie->core_apb_rst);
1418 dev_err(pcie->dev, "Failed to deassert core APB reset: %d\n",
1423 if (en_hw_hot_rst || pcie->of_data->has_sbr_reset_fix) {
1425 val = appl_readl(pcie, APPL_CTRL);
1431 appl_writel(pcie, val, APPL_CTRL);
1434 ret = tegra_pcie_enable_phy(pcie);
1436 dev_err(pcie->dev, "Failed to enable PHY: %d\n", ret);
1441 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK,
1445 appl_writel(pcie, APPL_DM_TYPE_RP, APPL_DM_TYPE);
1447 appl_writel(pcie, 0x0, APPL_CFG_SLCG_OVERRIDE);
1449 val = appl_readl(pcie, APPL_CTRL);
1450 appl_writel(pcie, val | APPL_CTRL_SYS_PRE_DET_STATE, APPL_CTRL);
1452 val = appl_readl(pcie, APPL_CFG_MISC);
1454 appl_writel(pcie, val, APPL_CFG_MISC);
1456 if (pcie->enable_srns || pcie->enable_ext_refclk) {
1463 val = appl_readl(pcie, APPL_PINMUX);
1466 appl_writel(pcie, val, APPL_PINMUX);
1469 if (!pcie->supports_clkreq) {
1470 val = appl_readl(pcie, APPL_PINMUX);
1473 appl_writel(pcie, val, APPL_PINMUX);
1477 appl_writel(pcie,
1478 pcie->atu_dma_res->start & APPL_CFG_IATU_DMA_BASE_ADDR_MASK,
1481 reset_control_deassert(pcie->core_rst);
1486 reset_control_assert(pcie->core_apb_rst);
1488 clk_disable_unprepare(pcie->core_clk);
1490 regulator_disable(pcie->pex_ctl_supply);
1492 tegra_pcie_disable_slot_regulators(pcie);
1494 if (pcie->enable_ext_refclk)
1495 tegra_pcie_bpmp_set_pll_state(pcie, false);
1497 tegra_pcie_bpmp_set_ctrl_state(pcie, false);
1502 static void tegra_pcie_unconfig_controller(struct tegra_pcie_dw *pcie)
1506 ret = reset_control_assert(pcie->core_rst);
1508 dev_err(pcie->dev, "Failed to assert \"core\" reset: %d\n", ret);
1510 tegra_pcie_disable_phy(pcie);
1512 ret = reset_control_assert(pcie->core_apb_rst);
1514 dev_err(pcie->dev, "Failed to assert APB reset: %d\n", ret);
1516 clk_disable_unprepare(pcie->core_clk);
1518 ret = regulator_disable(pcie->pex_ctl_supply);
1520 dev_err(pcie->dev, "Failed to disable regulator: %d\n", ret);
1522 tegra_pcie_disable_slot_regulators(pcie);
1524 if (pcie->enable_ext_refclk) {
1525 ret = tegra_pcie_bpmp_set_pll_state(pcie, false);
1527 dev_err(pcie->dev, "Failed to deinit UPHY: %d\n", ret);
1530 ret = tegra_pcie_bpmp_set_ctrl_state(pcie, false);
1532 dev_err(pcie->dev, "Failed to disable controller %d: %d\n",
1533 pcie->cid, ret);
1536 static int tegra_pcie_init_controller(struct tegra_pcie_dw *pcie)
1538 struct dw_pcie *pci = &pcie->pci;
1542 ret = tegra_pcie_config_controller(pcie, false);
1550 dev_err(pcie->dev, "Failed to add PCIe port: %d\n", ret);
1557 tegra_pcie_unconfig_controller(pcie);
1561 static int tegra_pcie_try_link_l2(struct tegra_pcie_dw *pcie)
1565 if (!tegra_pcie_dw_link_up(&pcie->pci))
1568 val = appl_readl(pcie, APPL_RADM_STATUS);
1570 appl_writel(pcie, val, APPL_RADM_STATUS);
1572 return readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, val,
1577 static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)
1582 if (!tegra_pcie_dw_link_up(&pcie->pci)) {
1583 dev_dbg(pcie->dev, "PCIe link is not up...!\n");
1595 appl_writel(pcie, 0x0, APPL_INTR_EN_L0_0);
1597 if (tegra_pcie_try_link_l2(pcie)) {
1598 dev_info(pcie->dev, "Link didn't transition to L2 state\n");
1605 data = appl_readl(pcie, APPL_PINMUX);
1607 appl_writel(pcie, data, APPL_PINMUX);
1613 data = readl(pcie->appl_base + APPL_CTRL);
1615 writel(data, pcie->appl_base + APPL_CTRL);
1617 err = readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG,
1625 dev_info(pcie->dev, "Link didn't go to detect state\n");
1631 data = appl_readl(pcie, APPL_PINMUX);
1636 appl_writel(pcie, data, APPL_PINMUX);
1639 static void tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie)
1641 tegra_pcie_downstream_dev_to_D0(pcie);
1642 dw_pcie_host_deinit(&pcie->pci.pp);
1643 tegra_pcie_dw_pme_turnoff(pcie);
1644 tegra_pcie_unconfig_controller(pcie);
1647 static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie)
1649 struct device *dev = pcie->dev;
1668 ret = tegra_pcie_init_controller(pcie);
1674 pcie->link_state = tegra_pcie_dw_link_up(&pcie->pci);
1675 if (!pcie->link_state) {
1686 pcie->debugfs = debugfs_create_dir(name, NULL);
1687 init_debugfs(pcie);
1692 tegra_pcie_deinit_controller(pcie);
1699 static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie)
1704 if (pcie->ep_state == EP_STATE_DISABLED)
1708 val = appl_readl(pcie, APPL_CTRL);
1710 appl_writel(pcie, val, APPL_CTRL);
1712 ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val,
1718 dev_err(pcie->dev, "Failed to go Detect state: %d\n", ret);
1720 reset_control_assert(pcie->core_rst);
1722 tegra_pcie_disable_phy(pcie);
1724 reset_control_assert(pcie->core_apb_rst);
1726 clk_disable_unprepare(pcie->core_clk);
1728 pm_runtime_put_sync(pcie->dev);
1730 if (pcie->enable_ext_refclk) {
1731 ret = tegra_pcie_bpmp_set_pll_state(pcie, false);
1733 dev_err(pcie->dev, "Failed to turn off UPHY: %d\n",
1737 ret = tegra_pcie_bpmp_set_pll_state(pcie, false);
1739 dev_err(pcie->dev, "Failed to turn off UPHY: %d\n", ret);
1741 pcie->ep_state = EP_STATE_DISABLED;
1742 dev_dbg(pcie->dev, "Uninitialization of endpoint is completed\n");
1745 static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
1747 struct dw_pcie *pci = &pcie->pci;
1749 struct device *dev = pcie->dev;
1754 if (pcie->ep_state == EP_STATE_ENABLED)
1764 ret = tegra_pcie_bpmp_set_ctrl_state(pcie, true);
1766 dev_err(pcie->dev, "Failed to enable controller %u: %d\n",
1767 pcie->cid, ret);
1771 if (pcie->enable_ext_refclk) {
1772 ret = tegra_pcie_bpmp_set_pll_state(pcie, true);
1780 ret = clk_prepare_enable(pcie->core_clk);
1786 ret = reset_control_deassert(pcie->core_apb_rst);
1792 ret = tegra_pcie_enable_phy(pcie);
1799 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0);
1800 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0);
1801 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1);
1802 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2);
1803 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3);
1804 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6);
1805 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7);
1806 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0);
1807 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9);
1808 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10);
1809 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11);
1810 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13);
1811 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14);
1812 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15);
1813 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17);
1816 val = appl_readl(pcie, APPL_DM_TYPE);
1819 appl_writel(pcie, val, APPL_DM_TYPE);
1821 appl_writel(pcie, 0x0, APPL_CFG_SLCG_OVERRIDE);
1823 val = appl_readl(pcie, APPL_CTRL);
1826 appl_writel(pcie, val, APPL_CTRL);
1828 val = appl_readl(pcie, APPL_CFG_MISC);
1831 appl_writel(pcie, val, APPL_CFG_MISC);
1833 val = appl_readl(pcie, APPL_PINMUX);
1836 appl_writel(pcie, val, APPL_PINMUX);
1838 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK,
1841 appl_writel(pcie, pcie->atu_dma_res->start &
1845 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
1849 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
1851 val = appl_readl(pcie, APPL_INTR_EN_L1_0_0);
1854 appl_writel(pcie, val, APPL_INTR_EN_L1_0_0);
1856 reset_control_deassert(pcie->core_rst);
1858 if (pcie->update_fc_fixup) {
1864 config_gen3_gen4_eq_presets(pcie);
1866 init_host_aspm(pcie);
1869 if (!pcie->supports_clkreq) {
1870 disable_aspm_l11(pcie);
1871 disable_aspm_l12(pcie);
1874 if (!pcie->of_data->has_l1ss_exit_fix) {
1880 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
1884 if (pcie->enable_srns) {
1885 val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
1888 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA,
1892 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
1909 if (pcie->of_data->has_ltr_req_fix) {
1910 val = appl_readl(pcie, APPL_LTR_MSG_2);
1912 appl_writel(pcie, val, APPL_LTR_MSG_2);
1916 val = appl_readl(pcie, APPL_CTRL);
1918 appl_writel(pcie, val, APPL_CTRL);
1920 pcie->ep_state = EP_STATE_ENABLED;
1926 reset_control_assert(pcie->core_rst);
1927 tegra_pcie_disable_phy(pcie);
1929 reset_control_assert(pcie->core_apb_rst);
1931 clk_disable_unprepare(pcie->core_clk);
1933 tegra_pcie_bpmp_set_pll_state(pcie, false);
1935 tegra_pcie_bpmp_set_ctrl_state(pcie, false);
1942 struct tegra_pcie_dw *pcie = arg;
1944 if (gpiod_get_value(pcie->pex_rst_gpiod))
1945 pex_ep_event_pex_rst_assert(pcie);
1947 pex_ep_event_pex_rst_deassert(pcie);
1952 static int tegra_pcie_ep_raise_legacy_irq(struct tegra_pcie_dw *pcie, u16 irq)
1958 appl_writel(pcie, 1, APPL_LEGACY_INTX);
1960 appl_writel(pcie, 0, APPL_LEGACY_INTX);
1964 static int tegra_pcie_ep_raise_msi_irq(struct tegra_pcie_dw *pcie, u16 irq)
1969 appl_writel(pcie, BIT(irq), APPL_MSI_CTRL_1);
1974 static int tegra_pcie_ep_raise_msix_irq(struct tegra_pcie_dw *pcie, u16 irq)
1976 struct dw_pcie_ep *ep = &pcie->pci.ep;
1988 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
1992 return tegra_pcie_ep_raise_legacy_irq(pcie, interrupt_num);
1995 return tegra_pcie_ep_raise_msi_irq(pcie, interrupt_num);
1998 return tegra_pcie_ep_raise_msix_irq(pcie, interrupt_num);
2029 static int tegra_pcie_config_ep(struct tegra_pcie_dw *pcie,
2032 struct dw_pcie *pci = &pcie->pci;
2033 struct device *dev = pcie->dev;
2043 ret = gpiod_set_debounce(pcie->pex_rst_gpiod, PERST_DEBOUNCE_TIME);
2050 ret = gpiod_to_irq(pcie->pex_rst_gpiod);
2055 pcie->pex_rst_irq = (unsigned int)ret;
2058 pcie->cid);
2064 irq_set_status_flags(pcie->pex_rst_irq, IRQ_NOAUTOEN);
2066 pcie->ep_state = EP_STATE_DISABLED;
2068 ret = devm_request_threaded_irq(dev, pcie->pex_rst_irq, NULL,
2072 name, (void *)pcie);
2096 struct tegra_pcie_dw *pcie;
2106 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
2107 if (!pcie)
2110 pci = &pcie->pci;
2113 pcie->dev = &pdev->dev;
2114 pcie->of_data = (struct tegra_pcie_dw_of_data *)data;
2115 pci->n_fts[0] = pcie->of_data->n_fts[0];
2116 pci->n_fts[1] = pcie->of_data->n_fts[1];
2120 ret = tegra_pcie_dw_parse_dt(pcie);
2133 ret = tegra_pcie_get_slot_regulators(pcie);
2146 if (pcie->pex_refclk_sel_gpiod)
2147 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 1);
2149 pcie->pex_ctl_supply = devm_regulator_get(dev, "vddio-pex-ctl");
2150 if (IS_ERR(pcie->pex_ctl_supply)) {
2151 ret = PTR_ERR(pcie->pex_ctl_supply);
2154 PTR_ERR(pcie->pex_ctl_supply));
2158 pcie->core_clk = devm_clk_get(dev, "core");
2159 if (IS_ERR(pcie->core_clk)) {
2161 PTR_ERR(pcie->core_clk));
2162 return PTR_ERR(pcie->core_clk);
2165 pcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2167 if (!pcie->appl_res) {
2172 pcie->appl_base = devm_ioremap_resource(dev, pcie->appl_res);
2173 if (IS_ERR(pcie->appl_base))
2174 return PTR_ERR(pcie->appl_base);
2176 pcie->core_apb_rst = devm_reset_control_get(dev, "apb");
2177 if (IS_ERR(pcie->core_apb_rst)) {
2179 PTR_ERR(pcie->core_apb_rst));
2180 return PTR_ERR(pcie->core_apb_rst);
2183 phys = devm_kcalloc(dev, pcie->phy_count, sizeof(*phys), GFP_KERNEL);
2187 for (i = 0; i < pcie->phy_count; i++) {
2203 pcie->phys = phys;
2211 pcie->atu_dma_res = atu_dma_res;
2218 pcie->core_rst = devm_reset_control_get(dev, "core");
2219 if (IS_ERR(pcie->core_rst)) {
2221 PTR_ERR(pcie->core_rst));
2222 return PTR_ERR(pcie->core_rst);
2229 pcie->bpmp = tegra_bpmp_get(dev);
2230 if (IS_ERR(pcie->bpmp))
2231 return PTR_ERR(pcie->bpmp);
2233 platform_set_drvdata(pdev, pcie);
2235 pcie->icc_path = devm_of_icc_get(&pdev->dev, "write");
2236 ret = PTR_ERR_OR_ZERO(pcie->icc_path);
2238 tegra_bpmp_put(pcie->bpmp);
2243 switch (pcie->of_data->mode) {
2246 IRQF_SHARED, "tegra-pcie-intr", pcie);
2253 ret = tegra_pcie_config_rp(pcie);
2265 "tegra-pcie-ep-intr", pcie);
2272 ret = tegra_pcie_config_ep(pcie, pdev);
2279 pcie->of_data->mode);
2283 tegra_bpmp_put(pcie->bpmp);
2289 struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev);
2291 if (pcie->of_data->mode == DW_PCIE_RC_TYPE) {
2292 if (!pcie->link_state)
2295 debugfs_remove_recursive(pcie->debugfs);
2296 tegra_pcie_deinit_controller(pcie);
2297 pm_runtime_put_sync(pcie->dev);
2299 disable_irq(pcie->pex_rst_irq);
2300 pex_ep_event_pex_rst_assert(pcie);
2303 pm_runtime_disable(pcie->dev);
2304 tegra_bpmp_put(pcie->bpmp);
2305 if (pcie->pex_refclk_sel_gpiod)
2306 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 0);
2311 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
2314 if (pcie->of_data->mode == DW_PCIE_EP_TYPE) {
2319 if (!pcie->link_state)
2323 if (!pcie->of_data->has_sbr_reset_fix) {
2324 val = appl_readl(pcie, APPL_CTRL);
2328 appl_writel(pcie, val, APPL_CTRL);
2336 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
2338 if (!pcie->link_state)
2341 tegra_pcie_downstream_dev_to_D0(pcie);
2342 tegra_pcie_dw_pme_turnoff(pcie);
2343 tegra_pcie_unconfig_controller(pcie);
2350 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
2353 if (!pcie->link_state)
2356 ret = tegra_pcie_config_controller(pcie, true);
2360 ret = tegra_pcie_dw_host_init(&pcie->pci.pp);
2366 dw_pcie_setup_rc(&pcie->pci.pp);
2368 ret = tegra_pcie_dw_start_link(&pcie->pci);
2375 tegra_pcie_unconfig_controller(pcie);
2381 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
2384 if (pcie->of_data->mode == DW_PCIE_EP_TYPE) {
2389 if (!pcie->link_state)
2393 if (!pcie->of_data->has_sbr_reset_fix) {
2394 val = appl_readl(pcie, APPL_CTRL);
2400 appl_writel(pcie, val, APPL_CTRL);
2408 struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev);
2410 if (pcie->of_data->mode == DW_PCIE_RC_TYPE) {
2411 if (!pcie->link_state)
2414 debugfs_remove_recursive(pcie->debugfs);
2415 tegra_pcie_downstream_dev_to_D0(pcie);
2417 disable_irq(pcie->pci.pp.irq);
2419 disable_irq(pcie->pci.pp.msi_irq[0]);
2421 tegra_pcie_dw_pme_turnoff(pcie);
2422 tegra_pcie_unconfig_controller(pcie);
2423 pm_runtime_put_sync(pcie->dev);
2425 disable_irq(pcie->pex_rst_irq);
2426 pex_ep_event_pex_rst_assert(pcie);
2473 .compatible = "nvidia,tegra194-pcie",
2477 .compatible = "nvidia,tegra194-pcie-ep",
2481 .compatible = "nvidia,tegra234-pcie",
2485 .compatible = "nvidia,tegra234-pcie-ep",
2503 .name = "tegra194-pcie",