Lines Matching refs:parf
236 void __iomem *parf; /* DT parf */
354 writel(1, pcie->parf + PARF_PHY_CTRL);
399 val = readl(pcie->parf + PARF_PHY_CTRL);
401 writel(val, pcie->parf + PARF_PHY_CTRL);
412 pcie->parf + PARF_PCS_DEEMPH);
415 pcie->parf + PARF_PCS_SWING);
416 writel(PHY_RX0_EQ(4), pcie->parf + PARF_CONFIG_BITS);
421 val = readl(pcie->parf + PARF_PHY_CTRL);
424 writel(val, pcie->parf + PARF_PHY_CTRL);
428 val = readl(pcie->parf + PARF_PHY_REFCLK);
433 writel(val, pcie->parf + PARF_PHY_REFCLK);
520 writel(0, pcie->parf + PARF_DBI_BASE_ADDR);
523 u32 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
526 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
539 val = readl(pcie->parf + PARF_LTSSM);
541 writel(val, pcie->parf + PARF_LTSSM);
606 val = readl(pcie->parf + PARF_PHY_CTRL);
608 writel(val, pcie->parf + PARF_PHY_CTRL);
611 writel(0, pcie->parf + PARF_DBI_BASE_ADDR);
614 val = readl(pcie->parf + PARF_SYS_CTRL);
616 writel(val, pcie->parf + PARF_SYS_CTRL);
618 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
620 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
622 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
624 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
660 res->resets[9].id = "parf";
803 writel(SLV_ADDR_SPACE_SZ, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE);
805 val = readl(pcie->parf + PARF_PHY_CTRL);
807 writel(val, pcie->parf + PARF_PHY_CTRL);
809 writel(0, pcie->parf + PARF_DBI_BASE_ADDR);
814 pcie->parf + PARF_SYS_CTRL);
815 writel(0, pcie->parf + PARF_Q2A_FLUSH);
925 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE);
928 val = readl(pcie->parf + PARF_PHY_CTRL);
930 writel(val, pcie->parf + PARF_PHY_CTRL);
933 writel(0, pcie->parf + PARF_DBI_BASE_ADDR);
936 val = readl(pcie->parf + PARF_SYS_CTRL);
938 writel(val, pcie->parf + PARF_SYS_CTRL);
940 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
942 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
945 val = readl(pcie->parf + PARF_PM_CTRL);
947 writel(val, pcie->parf + PARF_PM_CTRL);
949 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
951 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
987 void __iomem *bdf_to_sid_base = pcie->parf + PARF_BDF_TO_SID_TABLE_N;
999 val = readl(pcie->parf + PARF_BDF_TO_SID_CFG);
1001 writel(val, pcie->parf + PARF_BDF_TO_SID_CFG);
1122 pcie->parf + PARF_SLV_ADDR_SPACE_SIZE);
1124 val = readl(pcie->parf + PARF_PHY_CTRL);
1126 writel(val, pcie->parf + PARF_PHY_CTRL);
1128 writel(0, pcie->parf + PARF_DBI_BASE_ADDR);
1130 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE);
1132 pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
1140 pcie->parf + PARF_SYS_CTRL);
1142 writel(0, pcie->parf + PARF_Q2A_FLUSH);
1158 writel(0, pcie->parf + PARF_BDF_TO_SID_TABLE_N + (4 * i));
1490 pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf");
1491 if (IS_ERR(pcie->parf)) {
1492 ret = PTR_ERR(pcie->parf);