Lines Matching defs:pcie
27 #include <linux/phy/pcie.h>
35 #include "pcie-designware.h"
222 int (*get_resources)(struct qcom_pcie *pcie);
223 int (*init)(struct qcom_pcie *pcie);
224 int (*post_init)(struct qcom_pcie *pcie);
225 void (*deinit)(struct qcom_pcie *pcie);
226 void (*ltssm_enable)(struct qcom_pcie *pcie);
227 int (*config_sid)(struct qcom_pcie *pcie);
250 static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
252 gpiod_set_value_cansleep(pcie->reset, 1);
256 static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
260 gpiod_set_value_cansleep(pcie->reset, 0);
266 struct qcom_pcie *pcie = to_qcom_pcie(pci);
269 if (pcie->cfg->ops->ltssm_enable)
270 pcie->cfg->ops->ltssm_enable(pcie);
289 static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie)
294 val = readl(pcie->elbi + ELBI_SYS_CTRL);
296 writel(val, pcie->elbi + ELBI_SYS_CTRL);
299 static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
301 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
302 struct dw_pcie *pci = pcie->pci;
304 bool is_apq = of_device_is_compatible(dev->of_node, "qcom,pcie-apq8064");
347 static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
349 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
354 writel(1, pcie->parf + PARF_PHY_CTRL);
359 static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
361 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
362 struct dw_pcie *pci = pcie->pci;
389 static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie)
391 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
392 struct dw_pcie *pci = pcie->pci;
399 val = readl(pcie->parf + PARF_PHY_CTRL);
401 writel(val, pcie->parf + PARF_PHY_CTRL);
407 if (of_device_is_compatible(node, "qcom,pcie-ipq8064") ||
408 of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) {
412 pcie->parf + PARF_PCS_DEEMPH);
415 pcie->parf + PARF_PCS_SWING);
416 writel(PHY_RX0_EQ(4), pcie->parf + PARF_CONFIG_BITS);
419 if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
421 val = readl(pcie->parf + PARF_PHY_CTRL);
424 writel(val, pcie->parf + PARF_PHY_CTRL);
428 val = readl(pcie->parf + PARF_PHY_REFCLK);
430 if (!of_device_is_compatible(node, "qcom,pcie-apq8064"))
433 writel(val, pcie->parf + PARF_PHY_REFCLK);
444 qcom_pcie_clear_hpc(pcie->pci);
449 static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie)
451 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
452 struct dw_pcie *pci = pcie->pci;
473 static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie)
475 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
482 static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie)
484 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
485 struct dw_pcie *pci = pcie->pci;
517 static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie)
520 writel(0, pcie->parf + PARF_DBI_BASE_ADDR);
523 u32 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
526 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
529 qcom_pcie_clear_hpc(pcie->pci);
534 static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie)
539 val = readl(pcie->parf + PARF_LTSSM);
541 writel(val, pcie->parf + PARF_LTSSM);
544 static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie)
546 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
547 struct dw_pcie *pci = pcie->pci;
570 static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie)
572 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
578 static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie)
580 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
581 struct dw_pcie *pci = pcie->pci;
601 static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
606 val = readl(pcie->parf + PARF_PHY_CTRL);
608 writel(val, pcie->parf + PARF_PHY_CTRL);
611 writel(0, pcie->parf + PARF_DBI_BASE_ADDR);
614 val = readl(pcie->parf + PARF_SYS_CTRL);
616 writel(val, pcie->parf + PARF_SYS_CTRL);
618 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
620 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
622 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
624 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
626 qcom_pcie_clear_hpc(pcie->pci);
631 static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
633 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
634 struct dw_pcie *pci = pcie->pci;
636 bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019");
644 /* qcom,pcie-ipq4019 is defined without "iface" */
673 static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie)
675 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
681 static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
683 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
684 struct dw_pcie *pci = pcie->pci;
713 static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie)
715 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
716 struct dw_pcie *pci = pcie->pci;
745 static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie)
747 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
752 static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
754 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
755 struct dw_pcie *pci = pcie->pci;
797 static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie)
799 struct dw_pcie *pci = pcie->pci;
803 writel(SLV_ADDR_SPACE_SZ, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE);
805 val = readl(pcie->parf + PARF_PHY_CTRL);
807 writel(val, pcie->parf + PARF_PHY_CTRL);
809 writel(0, pcie->parf + PARF_DBI_BASE_ADDR);
814 pcie->parf + PARF_SYS_CTRL);
815 writel(0, pcie->parf + PARF_Q2A_FLUSH);
835 static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
837 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
838 struct dw_pcie *pci = pcie->pci;
889 static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
891 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
892 struct dw_pcie *pci = pcie->pci;
925 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE);
928 val = readl(pcie->parf + PARF_PHY_CTRL);
930 writel(val, pcie->parf + PARF_PHY_CTRL);
933 writel(0, pcie->parf + PARF_DBI_BASE_ADDR);
936 val = readl(pcie->parf + PARF_SYS_CTRL);
938 writel(val, pcie->parf + PARF_SYS_CTRL);
940 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
942 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
945 val = readl(pcie->parf + PARF_PM_CTRL);
947 writel(val, pcie->parf + PARF_PM_CTRL);
949 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
951 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
962 static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
964 qcom_pcie_clear_hpc(pcie->pci);
969 static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie)
971 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
978 static int qcom_pcie_config_sid_1_9_0(struct qcom_pcie *pcie)
987 void __iomem *bdf_to_sid_base = pcie->parf + PARF_BDF_TO_SID_TABLE_N;
988 struct device *dev = pcie->pci->dev;
999 val = readl(pcie->parf + PARF_BDF_TO_SID_CFG);
1001 writel(val, pcie->parf + PARF_BDF_TO_SID_CFG);
1054 static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie)
1056 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
1057 struct dw_pcie *pci = pcie->pci;
1078 static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie)
1080 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
1085 static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie)
1087 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
1088 struct device *dev = pcie->pci->dev;
1114 static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
1116 struct dw_pcie *pci = pcie->pci;
1122 pcie->parf + PARF_SLV_ADDR_SPACE_SIZE);
1124 val = readl(pcie->parf + PARF_PHY_CTRL);
1126 writel(val, pcie->parf + PARF_PHY_CTRL);
1128 writel(0, pcie->parf + PARF_DBI_BASE_ADDR);
1130 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE);
1132 pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
1140 pcie->parf + PARF_SYS_CTRL);
1142 writel(0, pcie->parf + PARF_Q2A_FLUSH);
1158 writel(0, pcie->parf + PARF_BDF_TO_SID_TABLE_N + (4 * i));
1174 struct qcom_pcie *pcie = to_qcom_pcie(pci);
1177 qcom_ep_reset_assert(pcie);
1179 ret = pcie->cfg->ops->init(pcie);
1183 ret = phy_set_mode_ext(pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC);
1187 ret = phy_power_on(pcie->phy);
1191 if (pcie->cfg->ops->post_init) {
1192 ret = pcie->cfg->ops->post_init(pcie);
1197 qcom_ep_reset_deassert(pcie);
1199 if (pcie->cfg->ops->config_sid) {
1200 ret = pcie->cfg->ops->config_sid(pcie);
1208 qcom_ep_reset_assert(pcie);
1210 phy_power_off(pcie->phy);
1212 pcie->cfg->ops->deinit(pcie);
1220 struct qcom_pcie *pcie = to_qcom_pcie(pci);
1222 qcom_ep_reset_assert(pcie);
1223 phy_power_off(pcie->phy);
1224 pcie->cfg->ops->deinit(pcie);
1342 static int qcom_pcie_icc_init(struct qcom_pcie *pcie)
1344 struct dw_pcie *pci = pcie->pci;
1347 pcie->icc_mem = devm_of_icc_get(pci->dev, "pcie-mem");
1348 if (IS_ERR(pcie->icc_mem))
1349 return PTR_ERR(pcie->icc_mem);
1356 * for the pcie-mem path.
1358 ret = icc_set_bw(pcie->icc_mem, 0, MBps_to_icc(250));
1368 static void qcom_pcie_icc_update(struct qcom_pcie *pcie)
1370 struct dw_pcie *pci = pcie->pci;
1375 if (!pcie->icc_mem)
1403 ret = icc_set_bw(pcie->icc_mem, 0, width * bw);
1412 struct qcom_pcie *pcie = (struct qcom_pcie *)dev_get_drvdata(s->private);
1415 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L0S));
1418 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L1));
1421 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1));
1424 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2));
1427 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L2));
1432 static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie)
1434 struct dw_pcie *pci = pcie->pci;
1442 pcie->debugfs = debugfs_create_dir(name, NULL);
1443 debugfs_create_devm_seqfile(dev, "link_transition_count", pcie->debugfs,
1451 struct qcom_pcie *pcie;
1463 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
1464 if (!pcie)
1480 pcie->pci = pci;
1482 pcie->cfg = pcie_cfg;
1484 pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
1485 if (IS_ERR(pcie->reset)) {
1486 ret = PTR_ERR(pcie->reset);
1490 pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf");
1491 if (IS_ERR(pcie->parf)) {
1492 ret = PTR_ERR(pcie->parf);
1496 pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi");
1497 if (IS_ERR(pcie->elbi)) {
1498 ret = PTR_ERR(pcie->elbi);
1505 pcie->mhi = devm_ioremap_resource(dev, res);
1506 if (IS_ERR(pcie->mhi)) {
1507 ret = PTR_ERR(pcie->mhi);
1512 pcie->phy = devm_phy_optional_get(dev, "pciephy");
1513 if (IS_ERR(pcie->phy)) {
1514 ret = PTR_ERR(pcie->phy);
1518 ret = qcom_pcie_icc_init(pcie);
1522 ret = pcie->cfg->ops->get_resources(pcie);
1528 ret = phy_init(pcie->phy);
1532 platform_set_drvdata(pdev, pcie);
1540 qcom_pcie_icc_update(pcie);
1542 if (pcie->mhi)
1543 qcom_pcie_init_debugfs(pcie);
1548 phy_exit(pcie->phy);
1558 struct qcom_pcie *pcie = dev_get_drvdata(dev);
1565 ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1));
1586 if (!dw_pcie_link_up(pcie->pci)) {
1587 qcom_pcie_host_deinit(&pcie->pci->pp);
1588 pcie->suspended = true;
1596 struct qcom_pcie *pcie = dev_get_drvdata(dev);
1599 if (pcie->suspended) {
1600 ret = qcom_pcie_host_init(&pcie->pci->pp);
1604 pcie->suspended = false;
1607 qcom_pcie_icc_update(pcie);
1613 { .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
1614 { .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
1615 { .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },
1616 { .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 },
1617 { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
1618 { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
1619 { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
1620 { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
1621 { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
1622 { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
1623 { .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },
1624 { .compatible = "qcom,pcie-sa8775p", .data = &cfg_1_9_0},
1625 { .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 },
1626 { .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 },
1627 { .compatible = "qcom,pcie-sc8280xp", .data = &cfg_1_9_0 },
1628 { .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 },
1629 { .compatible = "qcom,pcie-sdx55", .data = &cfg_1_9_0 },
1630 { .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 },
1631 { .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 },
1632 { .compatible = "qcom,pcie-sm8350", .data = &cfg_1_9_0 },
1633 { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },
1634 { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
1635 { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 },
1658 .name = "qcom-pcie",