Lines Matching defs:clks
156 struct clk_bulk_data clks[QCOM_PCIE_1_0_0_MAX_CLOCKS];
165 struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS];
174 struct clk_bulk_data clks[QCOM_PCIE_2_3_2_MAX_CLOCKS];
181 struct clk_bulk_data clks[QCOM_PCIE_2_3_3_MAX_CLOCKS];
188 struct clk_bulk_data clks[QCOM_PCIE_2_4_0_MAX_CLOCKS];
197 struct clk_bulk_data clks[QCOM_PCIE_2_7_0_MAX_CLOCKS];
205 struct clk_bulk_data clks[QCOM_PCIE_2_9_0_MAX_CLOCKS];
315 res->clks[0].id = "iface";
316 res->clks[1].id = "core";
317 res->clks[2].id = "phy";
318 res->clks[3].id = "aux";
319 res->clks[4].id = "ref";
322 ret = devm_clk_bulk_get(dev, 3, res->clks);
327 ret = devm_clk_bulk_get_optional(dev, 2, res->clks + 3);
351 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
403 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
460 res->clks[0].id = "iface";
461 res->clks[1].id = "aux";
462 res->clks[2].id = "master_bus";
463 res->clks[3].id = "slave_bus";
465 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
478 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
495 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
510 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
558 res->clks[0].id = "aux";
559 res->clks[1].id = "cfg";
560 res->clks[2].id = "bus_master";
561 res->clks[3].id = "bus_slave";
563 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
574 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
591 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
639 res->clks[0].id = "aux";
640 res->clks[1].id = "master_bus";
641 res->clks[2].id = "slave_bus";
642 res->clks[3].id = "iface";
647 ret = devm_clk_bulk_get(dev, res->num_clks, res->clks);
678 clk_bulk_disable_unprepare(res->num_clks, res->clks);
704 ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
720 res->clks[0].id = "iface";
721 res->clks[1].id = "axi_m";
722 res->clks[2].id = "axi_s";
723 res->clks[3].id = "ahb";
724 res->clks[4].id = "aux";
726 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
749 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
779 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
856 res->clks[idx++].id = "aux";
857 res->clks[idx++].id = "cfg";
858 res->clks[idx++].id = "bus_master";
859 res->clks[idx++].id = "bus_slave";
860 res->clks[idx++].id = "slave_q2a";
864 ret = devm_clk_bulk_get(dev, num_clks, res->clks);
868 res->clks[idx++].id = "tbu";
869 res->clks[idx++].id = "ddrss_sf_tbu";
870 res->clks[idx++].id = "aggre0";
871 res->clks[idx++].id = "aggre1";
872 res->clks[idx++].id = "noc_aggr";
873 res->clks[idx++].id = "noc_aggr_4";
874 res->clks[idx++].id = "noc_aggr_south_sf";
875 res->clks[idx++].id = "cnoc_qx";
876 res->clks[idx++].id = "sleep";
877 res->clks[idx++].id = "cnoc_sf_axi";
882 ret = devm_clk_bulk_get_optional(dev, num_opt_clks, res->clks + num_clks);
903 ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
955 clk_bulk_disable_unprepare(res->num_clks, res->clks);
973 clk_bulk_disable_unprepare(res->num_clks, res->clks);
1061 res->clks[0].id = "iface";
1062 res->clks[1].id = "axi_m";
1063 res->clks[2].id = "axi_s";
1064 res->clks[3].id = "axi_bridge";
1065 res->clks[4].id = "rchng";
1067 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
1082 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
1111 return clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);