Lines Matching defs:afp
80 static void fu740_pcie_assert_reset(struct fu740_pcie *afp)
83 gpiod_set_value_cansleep(afp->reset, 0);
85 writel_relaxed(0x0, afp->mgmt_base + PCIEX8MGMT_PERST_N);
88 static void fu740_pcie_deassert_reset(struct fu740_pcie *afp)
91 writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PERST_N);
93 gpiod_set_value_cansleep(afp->reset, 1);
96 static void fu740_pcie_power_on(struct fu740_pcie *afp)
98 gpiod_set_value_cansleep(afp->pwren, 1);
107 static void fu740_pcie_drive_reset(struct fu740_pcie *afp)
109 fu740_pcie_assert_reset(afp);
110 fu740_pcie_power_on(afp);
111 fu740_pcie_deassert_reset(afp);
115 const uint16_t wrdata, struct fu740_pcie *afp)
117 struct device *dev = afp->pci.dev;
126 phy_cr_para_addr = afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_ADDR;
127 phy_cr_para_wr_data = afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_WR_DATA;
128 phy_cr_para_wr_en = afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_WR_EN;
129 phy_cr_para_ack = afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_ACK;
131 phy_cr_para_addr = afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_ADDR;
132 phy_cr_para_wr_data = afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_WR_DATA;
133 phy_cr_para_wr_en = afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_WR_EN;
134 phy_cr_para_ack = afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_ACK;
155 static void fu740_pcie_init_phy(struct fu740_pcie *afp)
158 writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PHY0_CR_PARA_SEL);
159 writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_PHY1_CR_PARA_SEL);
168 fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE0_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
169 fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE1_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
170 fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE2_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
171 fu740_phyregwrite(0, PCIEX8MGMT_PHY_LANE3_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
172 fu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE0_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
173 fu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE1_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
174 fu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE2_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
175 fu740_phyregwrite(1, PCIEX8MGMT_PHY_LANE3_BASE, PCIEX8MGMT_PHY_INIT_VAL, afp);
181 struct fu740_pcie *afp = dev_get_drvdata(dev);
203 writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_APP_LTSSM_ENABLE);
240 struct fu740_pcie *afp = to_fu740_pcie(pci);
245 fu740_pcie_drive_reset(afp);
248 ret = clk_prepare_enable(afp->pcie_aux);
258 writel_relaxed(0x1, afp->mgmt_base + PCIEX8MGMT_APP_HOLD_PHY_RST);
261 ret = reset_control_deassert(afp->rst);
267 fu740_pcie_init_phy(afp);
270 clk_disable_unprepare(afp->pcie_aux);
272 writel_relaxed(0x0, afp->mgmt_base + PCIEX8MGMT_APP_HOLD_PHY_RST);
274 clk_prepare_enable(afp->pcie_aux);
276 writel_relaxed(0x4, afp->mgmt_base + PCIEX8MGMT_DEVICE_TYPE);
293 struct fu740_pcie *afp;
295 afp = devm_kzalloc(dev, sizeof(*afp), GFP_KERNEL);
296 if (!afp)
298 pci = &afp->pci;
305 afp->mgmt_base = devm_platform_ioremap_resource_byname(pdev, "mgmt");
306 if (IS_ERR(afp->mgmt_base))
307 return PTR_ERR(afp->mgmt_base);
310 afp->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
311 if (IS_ERR(afp->reset))
312 return dev_err_probe(dev, PTR_ERR(afp->reset), "unable to get reset-gpios\n");
314 afp->pwren = devm_gpiod_get_optional(dev, "pwren", GPIOD_OUT_LOW);
315 if (IS_ERR(afp->pwren))
316 return dev_err_probe(dev, PTR_ERR(afp->pwren), "unable to get pwren-gpios\n");
319 afp->pcie_aux = devm_clk_get(dev, "pcie_aux");
320 if (IS_ERR(afp->pcie_aux))
321 return dev_err_probe(dev, PTR_ERR(afp->pcie_aux),
325 afp->rst = devm_reset_control_get_exclusive(dev, NULL);
326 if (IS_ERR(afp->rst))
327 return dev_err_probe(dev, PTR_ERR(afp->rst), "unable to get reset\n");
329 platform_set_drvdata(pdev, afp);
336 struct fu740_pcie *afp = platform_get_drvdata(pdev);
339 fu740_pcie_assert_reset(afp);