Lines Matching refs:ctrl
129 unsigned int res, bit, ctrl;
134 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
135 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
138 pp->irq_mask[ctrl] |= BIT(bit);
139 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);
148 unsigned int res, bit, ctrl;
153 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
154 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
157 pp->irq_mask[ctrl] &= ~BIT(bit);
158 dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + res, pp->irq_mask[ctrl]);
167 unsigned int res, bit, ctrl;
169 ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
170 res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
261 u32 ctrl;
263 for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) {
264 if (pp->msi_irq[ctrl] > 0)
265 irq_set_chained_handler_and_data(pp->msi_irq[ctrl],
291 u32 ctrl, max_vectors;
295 for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++) {
298 msi_name[3] = '0' + ctrl;
307 pp->msi_irq[ctrl] = irq;
311 if (ctrl == 0)
314 max_vectors = ctrl * MAX_MSI_IRQS_PER_CTRL;
333 u32 ctrl, num_ctrls;
335 for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++)
336 pp->irq_mask[ctrl] = ~0;
365 for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
366 if (pp->msi_irq[ctrl] > 0)
367 irq_set_chained_handler_and_data(pp->msi_irq[ctrl],
737 u32 val, ctrl, num_ctrls;
752 for (ctrl = 0; ctrl < num_ctrls; ctrl++) {
754 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),
755 pp->irq_mask[ctrl]);
757 (ctrl * MSI_REG_CTRL_BLOCK_SIZE),