Lines Matching refs:val
227 static inline void meson_cfg_writel(struct meson_pcie *mp, u32 val, u32 reg)
229 writel(val, mp->cfg_base + reg);
241 u32 val;
243 val = meson_cfg_readl(mp, PCIE_CFG0);
244 val |= APP_LTSSM_ENABLE;
245 meson_cfg_writel(mp, val, PCIE_CFG0);
253 * dwc supports 2^(val+7) payload size, which val is 0~5 default to 1.
268 u32 val;
272 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
273 val &= ~PCI_EXP_DEVCTL_PAYLOAD;
274 dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
276 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
277 val |= PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size);
278 dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
284 u32 val;
288 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
289 val &= ~PCI_EXP_DEVCTL_READRQ;
290 dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
292 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
293 val |= PCIE_CAP_MAX_READ_REQ_SIZE(max_rd_req_size);
294 dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
308 int where, int size, u32 *val)
312 ret = pci_generic_config_read(bus, devfn, where, size, val);
323 *val = (*val & ((1 << (size * 8)) - 1)) << (8 * (where & 3));
324 *val &= ~0xffffff00;
325 *val |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
327 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);