Lines Matching refs:imx6_pcie
72 struct imx6_pcie {
157 static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
159 WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ &&
160 imx6_pcie->drvdata->variant != IMX8MQ_EP &&
161 imx6_pcie->drvdata->variant != IMX8MM &&
162 imx6_pcie->drvdata->variant != IMX8MM_EP &&
163 imx6_pcie->drvdata->variant != IMX8MP &&
164 imx6_pcie->drvdata->variant != IMX8MP_EP);
165 return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
168 static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
172 if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE)
177 switch (imx6_pcie->drvdata->variant) {
180 if (imx6_pcie->controller_id == 1) {
195 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val);
198 static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val)
200 struct dw_pcie *pci = imx6_pcie->pci;
219 static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
221 struct dw_pcie *pci = imx6_pcie->pci;
231 ret = pcie_phy_poll_ack(imx6_pcie, true);
238 return pcie_phy_poll_ack(imx6_pcie, false);
242 static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data)
244 struct dw_pcie *pci = imx6_pcie->pci;
248 ret = pcie_phy_wait_ack(imx6_pcie, addr);
256 ret = pcie_phy_poll_ack(imx6_pcie, true);
265 return pcie_phy_poll_ack(imx6_pcie, false);
268 static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data)
270 struct dw_pcie *pci = imx6_pcie->pci;
276 ret = pcie_phy_wait_ack(imx6_pcie, addr);
287 ret = pcie_phy_poll_ack(imx6_pcie, true);
296 ret = pcie_phy_poll_ack(imx6_pcie, false);
305 ret = pcie_phy_poll_ack(imx6_pcie, true);
314 ret = pcie_phy_poll_ack(imx6_pcie, false);
323 static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
325 switch (imx6_pcie->drvdata->variant) {
341 regmap_update_bits(imx6_pcie->iomuxc_gpr,
342 imx6_pcie_grp_offset(imx6_pcie),
350 if (imx6_pcie->vph &&
351 regulator_get_voltage(imx6_pcie->vph) > 3000000)
352 regmap_update_bits(imx6_pcie->iomuxc_gpr,
353 imx6_pcie_grp_offset(imx6_pcie),
358 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
362 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
367 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
371 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
374 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
376 imx6_pcie->tx_deemph_gen1 << 0);
377 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
379 imx6_pcie->tx_deemph_gen2_3p5db << 6);
380 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
382 imx6_pcie->tx_deemph_gen2_6db << 12);
383 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
385 imx6_pcie->tx_swing_full << 18);
386 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
388 imx6_pcie->tx_swing_low << 25);
392 imx6_pcie_configure_type(imx6_pcie);
395 static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
398 struct device *dev = imx6_pcie->pci->dev;
400 if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr,
408 static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie)
410 unsigned long phy_rate = clk_get_rate(imx6_pcie->pcie_phy);
414 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
433 dev_err(imx6_pcie->pci->dev,
438 pcie_phy_read(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val);
443 pcie_phy_write(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val);
445 pcie_phy_read(imx6_pcie, PCIE_PHY_ATEOVRD, &val);
450 pcie_phy_write(imx6_pcie, PCIE_PHY_ATEOVRD, val);
455 static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
459 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
462 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
465 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
469 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
472 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
513 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
520 imx6_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie");
521 if (IS_ERR(imx6_pcie->pd_pcie))
522 return PTR_ERR(imx6_pcie->pd_pcie);
524 if (!imx6_pcie->pd_pcie)
526 link = device_link_add(dev, imx6_pcie->pd_pcie,
535 imx6_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy");
536 if (IS_ERR(imx6_pcie->pd_pcie_phy))
537 return PTR_ERR(imx6_pcie->pd_pcie_phy);
539 link = device_link_add(dev, imx6_pcie->pd_pcie_phy,
551 static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
553 struct dw_pcie *pci = imx6_pcie->pci;
558 switch (imx6_pcie->drvdata->variant) {
560 ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
566 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
572 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
581 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
592 ret = clk_prepare_enable(imx6_pcie->pcie_aux);
598 offset = imx6_pcie_grp_offset(imx6_pcie);
603 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
606 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
615 static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie)
617 switch (imx6_pcie->drvdata->variant) {
619 clk_disable_unprepare(imx6_pcie->pcie_inbound_axi);
623 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
625 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
630 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
640 clk_disable_unprepare(imx6_pcie->pcie_aux);
647 static int imx6_pcie_clk_enable(struct imx6_pcie *imx6_pcie)
649 struct dw_pcie *pci = imx6_pcie->pci;
653 ret = clk_prepare_enable(imx6_pcie->pcie_phy);
659 ret = clk_prepare_enable(imx6_pcie->pcie_bus);
665 ret = clk_prepare_enable(imx6_pcie->pcie);
671 ret = imx6_pcie_enable_ref_clk(imx6_pcie);
682 clk_disable_unprepare(imx6_pcie->pcie);
684 clk_disable_unprepare(imx6_pcie->pcie_bus);
686 clk_disable_unprepare(imx6_pcie->pcie_phy);
691 static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie)
693 imx6_pcie_disable_ref_clk(imx6_pcie);
694 clk_disable_unprepare(imx6_pcie->pcie);
695 clk_disable_unprepare(imx6_pcie->pcie_bus);
696 clk_disable_unprepare(imx6_pcie->pcie_phy);
699 static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
701 switch (imx6_pcie->drvdata->variant) {
705 reset_control_assert(imx6_pcie->pciephy_reset);
711 reset_control_assert(imx6_pcie->apps_reset);
714 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
718 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
723 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
728 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
730 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
736 if (gpio_is_valid(imx6_pcie->reset_gpio))
737 gpio_set_value_cansleep(imx6_pcie->reset_gpio,
738 imx6_pcie->gpio_active_high);
741 static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
743 struct dw_pcie *pci = imx6_pcie->pci;
746 switch (imx6_pcie->drvdata->variant) {
749 reset_control_deassert(imx6_pcie->pciephy_reset);
752 reset_control_deassert(imx6_pcie->pciephy_reset);
758 if (likely(imx6_pcie->phy_base)) {
761 imx6_pcie->phy_base + PCIE_PHY_CMN_REG4);
765 imx6_pcie->phy_base + PCIE_PHY_CMN_REG24);
768 imx6_pcie->phy_base + PCIE_PHY_CMN_REG26);
773 imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie);
776 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
780 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
794 if (gpio_is_valid(imx6_pcie->reset_gpio)) {
796 gpio_set_value_cansleep(imx6_pcie->reset_gpio,
797 !imx6_pcie->gpio_active_high);
805 static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
807 struct dw_pcie *pci = imx6_pcie->pci;
826 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
828 switch (imx6_pcie->drvdata->variant) {
832 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
843 reset_control_deassert(imx6_pcie->apps_reset);
850 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
852 switch (imx6_pcie->drvdata->variant) {
856 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
866 reset_control_assert(imx6_pcie->apps_reset);
873 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
915 if (imx6_pcie->drvdata->flags &
926 ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
941 imx6_pcie->link_is_up = true;
947 imx6_pcie->link_is_up = false;
951 imx6_pcie_reset_phy(imx6_pcie);
967 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
970 if (imx6_pcie->vpcie) {
971 ret = regulator_enable(imx6_pcie->vpcie);
979 imx6_pcie_assert_core_reset(imx6_pcie);
980 imx6_pcie_init_phy(imx6_pcie);
982 ret = imx6_pcie_clk_enable(imx6_pcie);
988 if (imx6_pcie->phy) {
989 ret = phy_init(imx6_pcie->phy);
996 if (imx6_pcie->phy) {
997 ret = phy_power_on(imx6_pcie->phy);
1004 ret = imx6_pcie_deassert_core_reset(imx6_pcie);
1010 imx6_setup_phy_mpll(imx6_pcie);
1015 if (imx6_pcie->phy)
1016 phy_exit(imx6_pcie->phy);
1018 imx6_pcie_clk_disable(imx6_pcie);
1020 if (imx6_pcie->vpcie)
1021 regulator_disable(imx6_pcie->vpcie);
1028 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
1030 if (imx6_pcie->phy) {
1031 if (phy_power_off(imx6_pcie->phy))
1033 phy_exit(imx6_pcie->phy);
1035 imx6_pcie_clk_disable(imx6_pcie);
1037 if (imx6_pcie->vpcie)
1038 regulator_disable(imx6_pcie->vpcie);
1101 static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie,
1108 struct dw_pcie *pci = imx6_pcie->pci;
1116 switch (imx6_pcie->drvdata->variant) {
1146 static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie)
1148 struct device *dev = imx6_pcie->pci->dev;
1151 if (imx6_pcie->turnoff_reset) {
1152 reset_control_assert(imx6_pcie->turnoff_reset);
1153 reset_control_deassert(imx6_pcie->turnoff_reset);
1158 switch (imx6_pcie->drvdata->variant) {
1161 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
1164 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
1183 static void imx6_pcie_msi_save_restore(struct imx6_pcie *imx6_pcie, bool save)
1187 struct dw_pcie *pci = imx6_pcie->pci;
1193 imx6_pcie->msi_ctrl = val;
1196 val = imx6_pcie->msi_ctrl;
1205 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
1206 struct dw_pcie_rp *pp = &imx6_pcie->pci->pp;
1208 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND))
1211 imx6_pcie_msi_save_restore(imx6_pcie, true);
1212 imx6_pcie_pm_turnoff(imx6_pcie);
1213 imx6_pcie_stop_link(imx6_pcie->pci);
1222 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
1223 struct dw_pcie_rp *pp = &imx6_pcie->pci->pp;
1225 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND))
1231 imx6_pcie_msi_save_restore(imx6_pcie, false);
1234 if (imx6_pcie->link_is_up)
1235 imx6_pcie_start_link(imx6_pcie->pci);
1249 struct imx6_pcie *imx6_pcie;
1256 imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL);
1257 if (!imx6_pcie)
1268 imx6_pcie->pci = pci;
1269 imx6_pcie->drvdata = of_device_get_match_data(dev);
1281 imx6_pcie->phy_base = devm_ioremap_resource(dev, &res);
1282 if (IS_ERR(imx6_pcie->phy_base))
1283 return PTR_ERR(imx6_pcie->phy_base);
1291 imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
1292 imx6_pcie->gpio_active_high = of_property_read_bool(node,
1294 if (gpio_is_valid(imx6_pcie->reset_gpio)) {
1295 ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio,
1296 imx6_pcie->gpio_active_high ?
1304 } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) {
1305 return imx6_pcie->reset_gpio;
1309 imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus");
1310 if (IS_ERR(imx6_pcie->pcie_bus))
1311 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_bus),
1314 imx6_pcie->pcie = devm_clk_get(dev, "pcie");
1315 if (IS_ERR(imx6_pcie->pcie))
1316 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie),
1319 switch (imx6_pcie->drvdata->variant) {
1321 imx6_pcie->pcie_inbound_axi = devm_clk_get(dev,
1323 if (IS_ERR(imx6_pcie->pcie_inbound_axi))
1324 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_inbound_axi),
1329 imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux");
1330 if (IS_ERR(imx6_pcie->pcie_aux))
1331 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux),
1336 imx6_pcie->controller_id = 1;
1338 imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev,
1340 if (IS_ERR(imx6_pcie->pciephy_reset)) {
1342 return PTR_ERR(imx6_pcie->pciephy_reset);
1345 imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev,
1347 if (IS_ERR(imx6_pcie->apps_reset)) {
1349 return PTR_ERR(imx6_pcie->apps_reset);
1356 imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux");
1357 if (IS_ERR(imx6_pcie->pcie_aux))
1358 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux),
1360 imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev,
1362 if (IS_ERR(imx6_pcie->apps_reset))
1363 return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset),
1366 imx6_pcie->phy = devm_phy_get(dev, "pcie-phy");
1367 if (IS_ERR(imx6_pcie->phy))
1368 return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy),
1376 if (imx6_pcie->phy == NULL) {
1377 imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy");
1378 if (IS_ERR(imx6_pcie->pcie_phy))
1379 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_phy),
1385 imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff");
1386 if (IS_ERR(imx6_pcie->turnoff_reset)) {
1388 return PTR_ERR(imx6_pcie->turnoff_reset);
1392 imx6_pcie->iomuxc_gpr =
1393 syscon_regmap_lookup_by_compatible(imx6_pcie->drvdata->gpr);
1394 if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
1396 return PTR_ERR(imx6_pcie->iomuxc_gpr);
1401 &imx6_pcie->tx_deemph_gen1))
1402 imx6_pcie->tx_deemph_gen1 = 0;
1405 &imx6_pcie->tx_deemph_gen2_3p5db))
1406 imx6_pcie->tx_deemph_gen2_3p5db = 0;
1409 &imx6_pcie->tx_deemph_gen2_6db))
1410 imx6_pcie->tx_deemph_gen2_6db = 20;
1413 &imx6_pcie->tx_swing_full))
1414 imx6_pcie->tx_swing_full = 127;
1417 &imx6_pcie->tx_swing_low))
1418 imx6_pcie->tx_swing_low = 127;
1424 imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie");
1425 if (IS_ERR(imx6_pcie->vpcie)) {
1426 if (PTR_ERR(imx6_pcie->vpcie) != -ENODEV)
1427 return PTR_ERR(imx6_pcie->vpcie);
1428 imx6_pcie->vpcie = NULL;
1431 imx6_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph");
1432 if (IS_ERR(imx6_pcie->vph)) {
1433 if (PTR_ERR(imx6_pcie->vph) != -ENODEV)
1434 return PTR_ERR(imx6_pcie->vph);
1435 imx6_pcie->vph = NULL;
1438 platform_set_drvdata(pdev, imx6_pcie);
1444 if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE) {
1445 ret = imx6_add_pcie_ep(imx6_pcie, pdev);
1467 struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);
1470 imx6_pcie_assert_core_reset(imx6_pcie);
1573 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
1579 if (imx6_pcie->drvdata->dbi_length) {
1580 dev->cfg_size = imx6_pcie->drvdata->dbi_length;