Lines Matching defs:pcie
36 #include "pcie-designware.h"
80 struct clk *pcie;
97 /* power domain for pcie */
99 /* power domain for pcie phy */
370 /* configure constant input signal to the pcie ctrl and phy */
520 imx6_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie");
531 dev_err(dev, "Failed to add device_link to pcie pd.\n");
665 ret = clk_prepare_enable(imx6_pcie->pcie);
667 dev_err(dev, "unable to enable pcie clock\n");
673 dev_err(dev, "unable to enable pcie ref clock\n");
682 clk_disable_unprepare(imx6_pcie->pcie);
694 clk_disable_unprepare(imx6_pcie->pcie);
770 dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n");
984 dev_err(dev, "unable to enable pcie clocks: %d\n", ret);
991 dev_err(dev, "pcie PHY power up failed\n");
1006 dev_err(dev, "pcie deassert core reset failed: %d\n", ret);
1272 np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0);
1314 imx6_pcie->pcie = devm_clk_get(dev, "pcie");
1315 if (IS_ERR(imx6_pcie->pcie))
1316 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie),
1317 "pcie clock source missing or invalid\n");
1364 "failed to get pcie apps reset control\n");
1366 imx6_pcie->phy = devm_phy_get(dev, "pcie-phy");
1369 "failed to get pcie phy\n");
1533 { .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], },
1534 { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], },
1535 { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
1536 { .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], },
1537 { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], },
1538 { .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },
1539 { .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], },
1540 { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], },
1541 { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], },
1542 { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], },
1548 .name = "imx6q-pcie",