Lines Matching refs:dra7xx
3 * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
123 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
124 u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS);
131 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
134 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
136 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
141 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
150 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
152 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
157 static void dra7xx_pcie_enable_msi_interrupts(struct dra7xx_pcie *dra7xx)
159 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
162 dra7xx_pcie_writel(dra7xx,
167 static void dra7xx_pcie_enable_wrapper_interrupts(struct dra7xx_pcie *dra7xx)
169 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
171 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN,
175 static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
177 dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
178 dra7xx_pcie_enable_msi_interrupts(dra7xx);
184 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
186 dra7xx_pcie_enable_interrupts(dra7xx);
257 struct dra7xx_pcie *dra7xx;
267 dra7xx = to_dra7xx_pcie(pci);
269 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
270 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);
281 generic_handle_domain_irq(dra7xx->irq_domain, bit);
290 struct dra7xx_pcie *dra7xx = arg;
291 struct dw_pcie *pci = dra7xx->pci;
296 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN);
331 if (dra7xx->mode == DW_PCIE_EP_TYPE)
342 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg);
351 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
362 dra7xx->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
365 if (!dra7xx->irq_domain) {
380 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
386 dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
389 static void dra7xx_pcie_raise_legacy_irq(struct dra7xx_pcie *dra7xx)
391 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_ASSERT, 0x1);
393 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_DEASSERT, 0x1);
396 static void dra7xx_pcie_raise_msi_irq(struct dra7xx_pcie *dra7xx,
403 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_MSI_XMT, reg);
410 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
414 dra7xx_pcie_raise_legacy_irq(dra7xx);
417 dra7xx_pcie_raise_msi_irq(dra7xx, interrupt_num);
444 static int dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx,
450 struct dw_pcie *pci = dra7xx->pci;
473 static int dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
477 struct dw_pcie *pci = dra7xx->pci;
514 static void dra7xx_pcie_disable_phy(struct dra7xx_pcie *dra7xx)
516 int phy_count = dra7xx->phy_count;
519 phy_power_off(dra7xx->phy[phy_count]);
520 phy_exit(dra7xx->phy[phy_count]);
524 static int dra7xx_pcie_enable_phy(struct dra7xx_pcie *dra7xx)
526 int phy_count = dra7xx->phy_count;
531 ret = phy_set_mode(dra7xx->phy[i], PHY_MODE_PCIE);
535 ret = phy_init(dra7xx->phy[i]);
539 ret = phy_power_on(dra7xx->phy[i]);
541 phy_exit(dra7xx->phy[i]);
550 phy_power_off(dra7xx->phy[i]);
551 phy_exit(dra7xx->phy[i]);
616 * @dra7xx: the dra7xx device where the workaround should be applied
695 struct dra7xx_pcie *dra7xx;
711 dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
712 if (!dra7xx)
744 dra7xx->clk = devm_clk_get_optional(dev, NULL);
745 if (IS_ERR(dra7xx->clk))
746 return dev_err_probe(dev, PTR_ERR(dra7xx->clk),
749 ret = clk_prepare_enable(dra7xx->clk);
766 dra7xx->base = base;
767 dra7xx->phy = phy;
768 dra7xx->pci = pci;
769 dra7xx->phy_count = phy_count;
774 dra7xx->phy_count = 1; /* Fallback to x1 lane mode */
777 ret = dra7xx_pcie_enable_phy(dra7xx);
783 platform_set_drvdata(pdev, dra7xx);
799 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
801 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
810 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
817 ret = dra7xx_add_pcie_port(dra7xx, pdev);
827 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
834 ret = dra7xx_add_pcie_ep(dra7xx, pdev);
841 dra7xx->mode = mode;
844 IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
856 dra7xx_pcie_disable_phy(dra7xx);
867 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
868 struct dw_pcie *pci = dra7xx->pci;
871 if (dra7xx->mode != DW_PCIE_RC_TYPE)
884 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
885 struct dw_pcie *pci = dra7xx->pci;
888 if (dra7xx->mode != DW_PCIE_RC_TYPE)
901 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
903 dra7xx_pcie_disable_phy(dra7xx);
910 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
913 ret = dra7xx_pcie_enable_phy(dra7xx);
925 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
928 dra7xx_pcie_stop_link(dra7xx->pci);
935 dra7xx_pcie_disable_phy(dra7xx);
937 clk_disable_unprepare(dra7xx->clk);