Lines Matching defs:pcie
23 #include "pcie-cadence.h"
76 static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset)
78 return readl(pcie->user_cfg_base + offset);
81 static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset,
84 writel(value, pcie->user_cfg_base + offset);
87 static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset)
89 return readl(pcie->intd_cfg_base + offset);
92 static inline void j721e_pcie_intd_writel(struct j721e_pcie *pcie, u32 offset,
95 writel(value, pcie->intd_cfg_base + offset);
100 struct j721e_pcie *pcie = priv;
101 struct device *dev = pcie->cdns_pcie->dev;
104 reg = j721e_pcie_intd_readl(pcie, STATUS_REG_SYS_2);
105 if (!(reg & pcie->linkdown_irq_regfield))
110 j721e_pcie_intd_writel(pcie, STATUS_CLR_REG_SYS_2, pcie->linkdown_irq_regfield);
114 static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie)
118 reg = j721e_pcie_intd_readl(pcie, ENABLE_REG_SYS_2);
119 reg |= pcie->linkdown_irq_regfield;
120 j721e_pcie_intd_writel(pcie, ENABLE_REG_SYS_2, reg);
125 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
128 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS);
130 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg);
137 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
140 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS);
142 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg);
147 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);
150 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_LINKSTATUS);
164 static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon,
167 struct device *dev = pcie->cdns_pcie->dev;
169 u32 mode = pcie->mode;
178 dev_err(dev, "failed to set pcie mode\n");
183 static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie,
186 struct device *dev = pcie->cdns_pcie->dev;
204 static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,
207 struct device *dev = pcie->cdns_pcie->dev;
208 u32 lanes = pcie->num_lanes;
220 static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie)
222 struct device *dev = pcie->cdns_pcie->dev;
229 syscon = syscon_regmap_lookup_by_phandle(node, "ti,syscon-pcie-ctrl");
231 dev_err(dev, "Unable to get ti,syscon-pcie-ctrl regmap\n");
236 ret = of_parse_phandle_with_fixed_args(node, "ti,syscon-pcie-ctrl", 1,
241 ret = j721e_pcie_set_mode(pcie, syscon, offset);
247 ret = j721e_pcie_set_link_speed(pcie, syscon, offset);
253 ret = j721e_pcie_set_lane_count(pcie, syscon, offset);
326 .compatible = "ti,j721e-pcie-host",
330 .compatible = "ti,j721e-pcie-ep",
334 .compatible = "ti,j7200-pcie-host",
338 .compatible = "ti,j7200-pcie-ep",
342 .compatible = "ti,am64-pcie-host",
346 .compatible = "ti,am64-pcie-ep",
359 struct j721e_pcie *pcie;
376 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
377 if (!pcie)
395 cdns_pcie = &rc->pcie;
398 pcie->cdns_pcie = cdns_pcie;
411 cdns_pcie = &ep->pcie;
414 pcie->cdns_pcie = cdns_pcie;
421 pcie->mode = mode;
422 pcie->linkdown_irq_regfield = data->linkdown_irq_regfield;
427 pcie->intd_cfg_base = base;
432 pcie->user_cfg_base = base;
437 pcie->num_lanes = num_lanes;
446 dev_set_drvdata(dev, pcie);
454 ret = j721e_pcie_ctrl_init(pcie);
461 "j721e-pcie-link-down-irq", pcie);
467 j721e_pcie_config_link_irq(pcie);
497 pcie->refclk = clk;
514 clk_disable_unprepare(pcie->refclk);
547 struct j721e_pcie *pcie = platform_get_drvdata(pdev);
548 struct cdns_pcie *cdns_pcie = pcie->cdns_pcie;
551 clk_disable_unprepare(pcie->refclk);
561 .name = "j721e-pcie",