Lines Matching refs:port
2 /* Low-level parallel-port routines for 8255-based PC-style hardware.
43 * but rather will start at port->base_hi.
238 dev->port->irq != PARPORT_IRQ_NONE)
266 static size_t parport_pc_epp_read_data(struct parport *port, void *buf,
279 status = inb(STATUS(port));
285 insl(EPPDATA(port), buf, 4);
287 insb(EPPDATA(port), buf, 16);
293 *((char *)buf) = inb(EPPDATA(port));
298 status = inb(STATUS(port));
302 port->name);
303 clear_epp_timeout(port);
313 insl(EPPDATA(port), buf, (length >> 2));
316 insw(EPPDATA(port), buf, length >> 1);
318 insb(EPPDATA(port), buf, length);
319 if (inb(STATUS(port)) & 0x01) {
320 clear_epp_timeout(port);
326 *((char *)buf) = inb(EPPDATA(port));
328 if (inb(STATUS(port)) & 0x01) {
330 clear_epp_timeout(port);
338 static size_t parport_pc_epp_write_data(struct parport *port, const void *buf,
348 outsl(EPPDATA(port), buf, (length >> 2));
351 outsw(EPPDATA(port), buf, length >> 1);
353 outsb(EPPDATA(port), buf, length);
354 if (inb(STATUS(port)) & 0x01) {
355 clear_epp_timeout(port);
361 outb(*((char *)buf), EPPDATA(port));
363 if (inb(STATUS(port)) & 0x01) {
364 clear_epp_timeout(port);
372 static size_t parport_pc_epp_read_addr(struct parport *port, void *buf,
378 insb(EPPADDR(port), buf, length);
379 if (inb(STATUS(port)) & 0x01) {
380 clear_epp_timeout(port);
386 *((char *)buf) = inb(EPPADDR(port));
388 if (inb(STATUS(port)) & 0x01) {
389 clear_epp_timeout(port);
397 static size_t parport_pc_epp_write_addr(struct parport *port,
404 outsb(EPPADDR(port), buf, length);
405 if (inb(STATUS(port)) & 0x01) {
406 clear_epp_timeout(port);
412 outb(*((char *)buf), EPPADDR(port));
414 if (inb(STATUS(port)) & 0x01) {
415 clear_epp_timeout(port);
423 static size_t parport_pc_ecpepp_read_data(struct parport *port, void *buf,
428 frob_set_mode(port, ECR_EPP);
429 parport_pc_data_reverse(port);
430 parport_pc_write_control(port, 0x4);
431 got = parport_pc_epp_read_data(port, buf, length, flags);
432 frob_set_mode(port, ECR_PS2);
437 static size_t parport_pc_ecpepp_write_data(struct parport *port,
443 frob_set_mode(port, ECR_EPP);
444 parport_pc_write_control(port, 0x4);
445 parport_pc_data_forward(port);
446 written = parport_pc_epp_write_data(port, buf, length, flags);
447 frob_set_mode(port, ECR_PS2);
452 static size_t parport_pc_ecpepp_read_addr(struct parport *port, void *buf,
457 frob_set_mode(port, ECR_EPP);
458 parport_pc_data_reverse(port);
459 parport_pc_write_control(port, 0x4);
460 got = parport_pc_epp_read_addr(port, buf, length, flags);
461 frob_set_mode(port, ECR_PS2);
466 static size_t parport_pc_ecpepp_write_addr(struct parport *port,
472 frob_set_mode(port, ECR_EPP);
473 parport_pc_write_control(port, 0x4);
474 parport_pc_data_forward(port);
475 written = parport_pc_epp_write_addr(port, buf, length, flags);
476 frob_set_mode(port, ECR_PS2);
483 static size_t parport_pc_fifo_write_block_pio(struct parport *port,
489 unsigned long expire = jiffies + port->physport->cad->timeout;
490 const unsigned long fifo = FIFO(port);
492 const struct parport_pc_private *priv = port->physport->private_data;
495 port = port->physport;
498 parport_pc_disable_irq(port);
500 frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2));
503 parport_pc_data_forward(port); /* Must be in PS2 mode */
507 unsigned char ecrval = inb(ECONTROL(port));
511 /* Can't yield the port. */
514 /* Anyone else waiting for the port? */
515 if (port->waithead) {
516 printk(KERN_DEBUG "Somebody wants the port\n");
524 ECR_WRITE(port, ecrval & ~(1<<2));
526 ret = parport_wait_event(port, HZ);
535 ecrval = inb(ECONTROL(port));
548 expire = jiffies + port->cad->timeout;
567 ecrval = inb(ECONTROL(port));
576 dump_parport_state("leave fifo_write_block_pio", port);
581 static size_t parport_pc_fifo_write_block_dma(struct parport *port,
587 const struct parport_pc_private *priv = port->physport->private_data;
588 struct device *dev = port->physport->dev;
594 dump_parport_state("enter fifo_write_block_dma", port);
610 port = port->physport;
613 parport_pc_disable_irq(port);
615 frob_econtrol(port, (1<<4) | (1<<2), (1<<4) | (1<<2));
618 parport_pc_data_forward(port); /* Must be in PS2 mode */
621 unsigned long expire = jiffies + port->physport->cad->timeout;
632 disable_dma(port->dma);
633 clear_dma_ff(port->dma);
634 set_dma_mode(port->dma, DMA_MODE_WRITE);
635 set_dma_addr(port->dma, dma_addr);
636 set_dma_count(port->dma, count);
639 frob_econtrol(port, 1<<3, 1<<3);
642 frob_econtrol(port, 1<<2, 0);
644 enable_dma(port->dma);
655 ret = parport_wait_event(port, HZ);
665 if (!(inb(ECONTROL(port)) & (1<<2))) {
672 disable_dma(port->dma);
673 clear_dma_ff(port->dma);
674 count = get_dma_residue(port->dma);
677 cond_resched(); /* Can't yield the port. */
679 /* Anyone else waiting for the port? */
680 if (port->waithead) {
681 printk(KERN_DEBUG "Somebody wants the port\n");
694 disable_dma(port->dma);
695 clear_dma_ff(port->dma);
696 left += get_dma_residue(port->dma);
700 frob_econtrol(port, 1<<3, 0);
705 dump_parport_state("leave fifo_write_block_dma", port);
710 static inline size_t parport_pc_fifo_write_block(struct parport *port,
714 if (port->dma != PARPORT_DMA_NONE)
715 return parport_pc_fifo_write_block_dma(port, buf, length);
717 return parport_pc_fifo_write_block_pio(port, buf, length);
721 static size_t parport_pc_compat_write_block_pio(struct parport *port,
728 const struct parport_pc_private *priv = port->physport->private_data;
732 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
733 return parport_ieee1284_write_compat(port, buf,
736 /* Set up parallel port FIFO mode.*/
737 parport_pc_data_forward(port); /* Must be in PS2 mode */
738 parport_pc_frob_control(port, PARPORT_CONTROL_STROBE, 0);
739 r = change_mode(port, ECR_PPF); /* Parallel port FIFO */
742 port->name);
744 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
747 written = parport_pc_fifo_write_block(port, buf, length);
757 r = change_mode(port, ECR_PS2);
763 printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name);
766 frob_set_mode(port, ECR_TST);
770 if (inb(ECONTROL(port)) & 0x2) {
774 outb(0, FIFO(port));
778 frob_set_mode(port, ECR_PS2);
781 r = parport_wait_peripheral(port,
786 port->name, r);
788 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
795 static size_t parport_pc_ecp_write_block_pio(struct parport *port,
802 const struct parport_pc_private *priv = port->physport->private_data;
806 if (port->physport->cad->timeout <= PARPORT_INACTIVITY_O_NONBLOCK)
807 return parport_ieee1284_ecp_write_data(port, buf,
811 if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) {
813 parport_frob_control(port,
820 r = parport_wait_peripheral(port,
825 port->name, r);
829 /* Set up ECP parallel port mode.*/
830 parport_pc_data_forward(port); /* Must be in PS2 mode */
831 parport_pc_frob_control(port,
835 r = change_mode(port, ECR_ECP); /* ECP FIFO */
838 port->name);
839 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA;
842 written = parport_pc_fifo_write_block(port, buf, length);
852 r = change_mode(port, ECR_PS2);
858 printk(KERN_DEBUG "%s: FIFO is stuck\n", port->name);
861 frob_set_mode(port, ECR_TST);
865 if (inb(ECONTROL(port)) & 0x2) {
869 outb(0, FIFO(port));
873 frob_set_mode(port, ECR_PS2);
876 parport_pc_data_reverse(port); /* Must be in PS2 mode */
878 parport_frob_control(port, PARPORT_CONTROL_INIT, 0);
879 r = parport_wait_peripheral(port, PARPORT_STATUS_PAPEROUT, 0);
882 port->name, r);
884 parport_frob_control(port,
887 r = parport_wait_peripheral(port,
892 port->name, r);
895 r = parport_wait_peripheral(port,
900 port->name, r);
902 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE;
1349 printk(KERN_DEBUG "IT8705 Super-IO detection, now testing port 2E ...\n");
1408 * Checks for port existence, all ports support SPP MODE
1410 * 0 : No parallel port at this address
1411 * PARPORT_MODE_PCSPP : SPP port detected
1428 /* Do a simple read-write test to make sure the port exists. */
1449 * port here. */
1471 pr_info("parport 0x%lx: You gave this address, but there is probably no parallel port there!\n",
1538 * 0xff but any peripheral attached to the port may drag some or all of the
1686 printk(KERN_DEBUG "0x%lx: ECP port cfgA=0x%02x cfgB=0x%02x\n",
2085 priv->port = p;
2105 /* No port. */
2237 /* Done probing. Now put the port into a sensible start-up state. */
2240 * Put the ECP detected port in PS2 mode.
2248 /* Now that we've told the sharing engine about the port, and
2398 pr_debug("ITE887x: The PARALLEL I/O port is 0x%x\n", ite8872_lpt);
2412 pr_info("parport_pc: ITE 8872 parallel port: io=0x%X",
2500 /* Bit 5: EPP+ECP enable; bit 7: PS/2 bidirectional port enable */
2521 printk(KERN_DEBUG "parport_pc: Current parallel port base: 0x%X\n",
2526 printk(KERN_DEBUG "parport_pc: Parallel port base changed to 0x378\n");
2538 pr_info("parport_pc: VIA parallel port disabled in BIOS\n");
2591 pr_info("parport_pc: VIA parallel port: io=0x%X", port1);
2600 pr_warn("parport_pc: Strange, can't probe VIA parallel port: io=0x%X, irq=%d, dma=%d\n",
2835 /* Quatech SPPXP-100 Parallel port PCI ExpressCard */
2838 /* WCH CH382L PCI-E single parallel port card */
2909 printk(KERN_DEBUG "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx)\n",
2913 printk(KERN_DEBUG "PCI parallel port detected: %04x:%04x, I/O at %#lx(%#lx), IRQ %d\n",
3225 "Initialise mode for VIA VT8231 port (spp, ps2, epp, ecp or ecpepp)");
3392 struct parport *port;
3396 port = priv->port;
3397 dev = port->dev;
3398 parport_pc_unregister_port(port);
3405 MODULE_DESCRIPTION("PC-style parallel port driver");