Lines Matching defs:efuse
50 static void meson_mx_efuse_mask_bits(struct meson_mx_efuse *efuse, u32 reg,
55 data = readl(efuse->base + reg);
59 writel(data, efuse->base + reg);
62 static int meson_mx_efuse_hw_enable(struct meson_mx_efuse *efuse)
66 err = clk_prepare_enable(efuse->core_clk);
70 /* power up the efuse */
71 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
74 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL4,
80 static void meson_mx_efuse_hw_disable(struct meson_mx_efuse *efuse)
82 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
86 clk_disable_unprepare(efuse->core_clk);
89 static int meson_mx_efuse_read_addr(struct meson_mx_efuse *efuse,
97 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
101 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
104 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
108 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
111 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
118 readl(efuse->base + MESON_MX_EFUSE_CNTL1);
120 err = readl_poll_timeout_atomic(efuse->base + MESON_MX_EFUSE_CNTL1,
125 dev_err(efuse->config.dev,
126 "Timeout while reading efuse address %u\n", addr);
130 *value = readl(efuse->base + MESON_MX_EFUSE_CNTL2);
138 struct meson_mx_efuse *efuse = context;
142 err = meson_mx_efuse_hw_enable(efuse);
146 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
150 for (i = 0; i < bytes; i += efuse->config.word_size) {
151 addr = (offset + i) / efuse->config.word_size;
153 err = meson_mx_efuse_read_addr(efuse, addr, &tmp);
158 min_t(size_t, bytes - i, efuse->config.word_size));
161 meson_mx_efuse_mask_bits(efuse, MESON_MX_EFUSE_CNTL1,
164 meson_mx_efuse_hw_disable(efuse);
170 .name = "meson6-efuse",
175 .name = "meson8-efuse",
180 .name = "meson8b-efuse",
185 { .compatible = "amlogic,meson6-efuse", .data = &meson6_efuse_data },
186 { .compatible = "amlogic,meson8-efuse", .data = &meson8_efuse_data },
187 { .compatible = "amlogic,meson8b-efuse", .data = &meson8b_efuse_data },
195 struct meson_mx_efuse *efuse;
201 efuse = devm_kzalloc(&pdev->dev, sizeof(*efuse), GFP_KERNEL);
202 if (!efuse)
205 efuse->base = devm_platform_ioremap_resource(pdev, 0);
206 if (IS_ERR(efuse->base))
207 return PTR_ERR(efuse->base);
209 efuse->config.name = drvdata->name;
210 efuse->config.owner = THIS_MODULE;
211 efuse->config.dev = &pdev->dev;
212 efuse->config.priv = efuse;
213 efuse->config.stride = drvdata->word_size;
214 efuse->config.word_size = drvdata->word_size;
215 efuse->config.size = SZ_512;
216 efuse->config.read_only = true;
217 efuse->config.reg_read = meson_mx_efuse_read;
219 efuse->core_clk = devm_clk_get(&pdev->dev, "core");
220 if (IS_ERR(efuse->core_clk)) {
222 return PTR_ERR(efuse->core_clk);
225 efuse->nvmem = devm_nvmem_register(&pdev->dev, &efuse->config);
227 return PTR_ERR_OR_ZERO(efuse->nvmem);
233 .name = "meson-mx-efuse",