Lines Matching refs:base
27 #define IMX_OCOTP_OFFSET_B0W0 0x400 /* Offset from base address of the
82 void __iomem *base;
106 void __iomem *base = priv->base;
114 c = readl(base + IMX_OCOTP_ADDR_CTRL);
146 void __iomem *base = priv->base;
150 c = readl(base + IMX_OCOTP_ADDR_CTRL);
154 writel(bm_ctrl_error, base + IMX_OCOTP_ADDR_CTRL_CLR);
196 *(u32 *)buf = readl(priv->base + IMX_OCOTP_OFFSET_B0W0 +
281 timing = readl(priv->base + IMX_OCOTP_ADDR_TIMING) & 0x0FC00000;
286 writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
307 writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING);
375 ctrl = readl(priv->base + IMX_OCOTP_ADDR_CTRL);
380 writel(ctrl, priv->base + IMX_OCOTP_ADDR_CTRL);
408 writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
409 writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
410 writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
411 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0);
414 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA1);
415 writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
416 writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
417 writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
420 writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
421 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA2);
422 writel(0, priv->base + IMX_OCOTP_ADDR_DATA3);
423 writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
426 writel(0, priv->base + IMX_OCOTP_ADDR_DATA1);
427 writel(0, priv->base + IMX_OCOTP_ADDR_DATA2);
428 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA3);
429 writel(0, priv->base + IMX_OCOTP_ADDR_DATA0);
434 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0);
465 priv->base + IMX_OCOTP_ADDR_CTRL_SET);
609 priv->base = devm_platform_ioremap_resource(pdev, 0);
610 if (IS_ERR(priv->base))
611 return PTR_ERR(priv->base);