Lines Matching refs:value
37 u32 value, ul_intr_enable, dl_intr_enable;
50 value, (value & ul_intr_enable) != ul_intr_enable, 0,
65 value, (value & ul_intr_enable) != ul_intr_enable, 0,
74 value = ioread32(hw_info->pcie_base + DPMAIF_AO_UL_AP_L1TIMR0);
75 value |= DPMAIF_DL_INT_Q2APTOP | DPMAIF_DL_INT_Q2TOQ1;
76 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_UL_AP_L1TIMR0);
85 u32 value, ul_int_que_done;
94 value, (value & ul_int_que_done) == ul_int_que_done, 0,
99 value);
105 u32 value, ul_int_que_done;
114 value, (value & ul_int_que_done) != ul_int_que_done, 0,
119 value);
136 u32 value;
138 value = ioread32(hw_info->pcie_base + DPMAIF_AO_UL_AP_L2TIMR0);
140 return value;
145 u32 value, q_done;
151 ret = read_poll_timeout_atomic(t7xx_update_dlq_intr, value, value & q_done,
156 value);
228 unsigned long value;
230 value = FIELD_GET(DP_UL_INT_QDONE_MSK, intr_status);
231 if (value) {
234 t7xx_dpmaif_set_intr_para(para, DPF_INTR_UL_DONE, value);
236 for_each_set_bit(index, &value, DPMAIF_TXQ_NUM)
240 value = FIELD_GET(DP_UL_INT_EMPTY_MSK, intr_status);
241 if (value)
242 t7xx_dpmaif_set_intr_para(para, DPF_INTR_UL_DRB_EMPTY, value);
244 value = FIELD_GET(DP_UL_INT_MD_NOTREADY_MSK, intr_status);
245 if (value)
246 t7xx_dpmaif_set_intr_para(para, DPF_INTR_UL_MD_NOTREADY, value);
248 value = FIELD_GET(DP_UL_INT_MD_PWR_NOTREADY_MSK, intr_status);
249 if (value)
250 t7xx_dpmaif_set_intr_para(para, DPF_INTR_UL_MD_PWR_NOTREADY, value);
252 value = FIELD_GET(DP_UL_INT_ERR_MSK, intr_status);
253 if (value)
254 t7xx_dpmaif_set_intr_para(para, DPF_INTR_UL_LEN_ERR, value);
396 u32 value;
398 value = ioread32(hw_info->pcie_base + DPMAIF_AP_MEM_CLR);
399 value |= DPMAIF_MEM_CLR;
400 iowrite32(value, hw_info->pcie_base + DPMAIF_AP_MEM_CLR);
403 value, !(value & DPMAIF_MEM_CLR), 0,
459 unsigned int value;
461 value = DPMAIF_HPC_DLQ_PATH_MODE | DPMAIF_HPC_ADD_MODE_DF << 2;
462 value |= DPMAIF_HASH_PRIME_DF << 4;
463 value |= DPMAIF_HPC_TOTAL_NUM << 8;
464 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_DL_HPC_CNTL);
469 unsigned int value;
471 value = DPMAIF_AGG_MAX_LEN_DF | DPMAIF_AGG_TBL_ENT_NUM_DF << 16;
472 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_DL_DLQ_AGG_CFG);
488 unsigned int value, i;
492 value = FIELD_PREP(DPMAIF_DLQ_LOW_TIMEOUT_THRES_MKS, DPMAIF_DLQ_TIMEOUT_THRES_DF);
493 value |= FIELD_PREP(DPMAIF_DLQ_HIGH_TIMEOUT_THRES_MSK,
495 iowrite32(value,
517 u32 value, dl_bat_init = 0;
527 value, !(value & DPMAIF_DL_BAT_INIT_NOT_READY), 0,
537 value, !(value & DPMAIF_DL_BAT_INIT_NOT_READY), 0,
554 unsigned int value;
556 value = ioread32(hw_info->pcie_base + DPMAIF_DL_BAT_INIT_CON1);
557 value &= ~DPMAIF_BAT_SIZE_MSK;
558 value |= size & DPMAIF_BAT_SIZE_MSK;
559 iowrite32(value, hw_info->pcie_base + DPMAIF_DL_BAT_INIT_CON1);
564 unsigned int value;
566 value = ioread32(hw_info->pcie_base + DPMAIF_DL_BAT_INIT_CON1);
569 value |= DPMAIF_BAT_EN_MSK;
571 value &= ~DPMAIF_BAT_EN_MSK;
573 iowrite32(value, hw_info->pcie_base + DPMAIF_DL_BAT_INIT_CON1);
578 unsigned int value;
580 value = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_PKTINFO_CON0);
581 value &= ~DPMAIF_BAT_BID_MAXCNT_MSK;
582 value |= FIELD_PREP(DPMAIF_BAT_BID_MAXCNT_MSK, DPMAIF_HW_PKT_BIDCNT);
583 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_DL_PKTINFO_CON0);
593 unsigned int value;
595 value = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_PKTINFO_CON2);
596 value &= ~DPMAIF_PIT_CHK_NUM_MSK;
597 value |= FIELD_PREP(DPMAIF_PIT_CHK_NUM_MSK, DPMAIF_HW_CHK_PIT_NUM);
598 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_DL_PKTINFO_CON2);
603 unsigned int value;
605 value = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_PKTINFO_CON0);
606 value &= ~DPMAIF_BAT_REMAIN_MINSZ_MSK;
607 value |= FIELD_PREP(DPMAIF_BAT_REMAIN_MINSZ_MSK,
609 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_DL_PKTINFO_CON0);
614 unsigned int value;
616 value = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_PKTINFO_CON2);
617 value &= ~DPMAIF_BAT_BUF_SZ_MSK;
618 value |= FIELD_PREP(DPMAIF_BAT_BUF_SZ_MSK,
620 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_DL_PKTINFO_CON2);
625 unsigned int value;
627 value = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_PKTINFO_CON2);
628 value &= ~DPMAIF_BAT_RSV_LEN_MSK;
629 value |= DPMAIF_HW_BAT_RSVLEN;
630 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_DL_PKTINFO_CON2);
635 unsigned int value;
637 value = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_RDY_CHK_THRES);
638 value &= ~DPMAIF_PKT_ALIGN_MSK;
639 value |= DPMAIF_PKT_ALIGN_EN;
640 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_DL_RDY_CHK_THRES);
645 unsigned int value;
647 value = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_RDY_CHK_THRES);
648 value |= DPMAIF_DL_PKT_CHECKSUM_EN;
649 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_DL_RDY_CHK_THRES);
654 unsigned int value;
656 value = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_RDY_CHK_FRG_THRES);
657 value &= ~DPMAIF_FRG_CHECK_THRES_MSK;
658 value |= DPMAIF_HW_CHK_FRG_NUM;
659 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_DL_RDY_CHK_FRG_THRES);
664 unsigned int value;
666 value = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_RDY_CHK_FRG_THRES);
667 value &= ~DPMAIF_FRG_BUF_SZ_MSK;
668 value |= FIELD_PREP(DPMAIF_FRG_BUF_SZ_MSK,
670 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_DL_RDY_CHK_FRG_THRES);
675 unsigned int value;
677 value = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_RDY_CHK_FRG_THRES);
680 value |= DPMAIF_FRG_EN_MSK;
682 value &= ~DPMAIF_FRG_EN_MSK;
684 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_DL_RDY_CHK_FRG_THRES);
689 unsigned int value;
691 value = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_RDY_CHK_THRES);
692 value &= ~DPMAIF_BAT_CHECK_THRES_MSK;
693 value |= FIELD_PREP(DPMAIF_BAT_CHECK_THRES_MSK, DPMAIF_HW_CHK_BAT_NUM);
694 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_DL_RDY_CHK_THRES);
699 unsigned int value;
701 value = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_PIT_SEQ_END);
702 value &= ~DPMAIF_DL_PIT_SEQ_MSK;
703 value |= DPMAIF_DL_PIT_SEQ_VALUE;
704 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_DL_PIT_SEQ_END);
716 unsigned int value;
718 value = ioread32(hw_info->pcie_base + DPMAIF_DL_DLQPIT_INIT_CON1);
719 value &= ~DPMAIF_PIT_SIZE_MSK;
720 value |= size & DPMAIF_PIT_SIZE_MSK;
721 iowrite32(value, hw_info->pcie_base + DPMAIF_DL_DLQPIT_INIT_CON1);
730 unsigned int value;
732 value = ioread32(hw_info->pcie_base + DPMAIF_DL_DLQPIT_INIT_CON3);
733 value |= DPMAIF_DLQPIT_EN_MSK;
734 iowrite32(value, hw_info->pcie_base + DPMAIF_DL_DLQPIT_INIT_CON3);
742 u32 value;
749 value, !(value & DPMAIF_DL_PIT_INIT_NOT_READY),
759 value, !(value & DPMAIF_DL_PIT_INIT_NOT_READY),
785 u32 dl_bat_init, value;
788 value = ioread32(hw_info->pcie_base + DPMAIF_DL_BAT_INIT_CON1);
791 value |= DPMAIF_BAT_EN_MSK;
793 value &= ~DPMAIF_BAT_EN_MSK;
795 iowrite32(value, hw_info->pcie_base + DPMAIF_DL_BAT_INIT_CON1);
800 value, !(value & DPMAIF_DL_BAT_INIT_NOT_READY), 0,
807 value, !(value & DPMAIF_DL_BAT_INIT_NOT_READY), 0,
863 unsigned int value;
865 value = ioread32(hw_info->pcie_base + DPMAIF_UL_DRBSIZE_ADDRH_n(q_num));
866 value &= ~DPMAIF_DRB_SIZE_MSK;
867 value |= size & DPMAIF_DRB_SIZE_MSK;
868 iowrite32(value, hw_info->pcie_base + DPMAIF_UL_DRBSIZE_ADDRH_n(q_num));
881 u32 value;
883 value = ioread32(hw_info->pcie_base + DPMAIF_AO_UL_CHNL_ARB0);
886 value |= BIT(q_num);
888 value &= ~BIT(q_num);
890 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_UL_CHNL_ARB0);
896 u32 value;
898 value = ioread32(hw_info->pcie_base + DPMAIF_AO_UL_CHNL_ARB0);
901 value |= BIT(q_num + 8);
903 value &= ~BIT(q_num + 8);
905 iowrite32(value, hw_info->pcie_base + DPMAIF_AO_UL_CHNL_ARB0);
976 u32 ul_update, value;
983 value, !(value & DPMAIF_UL_ADD_NOT_READY), 0,
993 value, !(value & DPMAIF_UL_ADD_NOT_READY), 0,
1001 unsigned int value = ioread32(hw_info->pcie_base + DPMAIF_ULQ_STA0_n(q_num));
1003 return FIELD_GET(DPMAIF_UL_DRB_RIDX_MSK, value) / DPMAIF_UL_DRB_SIZE_WORD;
1009 u32 dl_update, value;
1016 value, !(value & DPMAIF_DL_ADD_NOT_READY), 0,
1026 value, !(value & DPMAIF_DL_ADD_NOT_READY), 0,
1039 u32 value;
1041 value = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_DLQ_WR_IDX +
1043 return value & DPMAIF_DL_RD_WR_IDX_MSK;
1048 u32 value;
1051 value, !(value & DPMAIF_DL_ADD_NOT_READY), 0,
1057 unsigned int value;
1064 value = bat_entry_cnt & DPMAIF_DL_ADD_COUNT_MASK;
1065 value |= DPMAIF_DL_ADD_UPDATE;
1066 iowrite32(value, hw_info->pcie_base + DPMAIF_DL_BAT_ADD);
1078 u32 value;
1080 value = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_BAT_RD_IDX);
1081 return value & DPMAIF_DL_RD_WR_IDX_MSK;
1086 u32 value;
1088 value = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_BAT_WR_IDX);
1089 return value & DPMAIF_DL_RD_WR_IDX_MSK;
1094 unsigned int value;
1101 value = frg_entry_cnt & DPMAIF_DL_ADD_COUNT_MASK;
1102 value |= DPMAIF_DL_FRG_ADD_UPDATE | DPMAIF_DL_ADD_UPDATE;
1103 iowrite32(value, hw_info->pcie_base + DPMAIF_DL_BAT_ADD);
1115 u32 value;
1117 value = ioread32(hw_info->pcie_base + DPMAIF_AO_DL_FRGBAT_RD_IDX);
1118 return value & DPMAIF_DL_RD_WR_IDX_MSK;