Lines Matching refs:ret
38 int ret;
49 ret = ioread32_poll_timeout_atomic(hw_info->pcie_base + DPMAIF_AO_UL_AP_L2TIMR0,
52 if (ret)
53 return ret;
64 ret = ioread32_poll_timeout_atomic(hw_info->pcie_base + DPMAIF_AO_UL_APDL_L2TIMR0,
67 if (ret)
68 return ret;
86 int ret;
93 ret = ioread32_poll_timeout_atomic(hw_info->pcie_base + DPMAIF_AO_UL_AP_L2TIMR0,
96 if (ret)
106 int ret;
113 ret = ioread32_poll_timeout_atomic(hw_info->pcie_base + DPMAIF_AO_UL_AP_L2TIMR0,
116 if (ret)
146 int ret;
151 ret = read_poll_timeout_atomic(t7xx_update_dlq_intr, value, value & q_done,
153 if (ret) {
422 int ret;
426 ret = t7xx_dpmaif_sram_init(hw_info);
427 if (ret)
428 return ret;
518 int ret;
526 ret = ioread32_poll_timeout_atomic(hw_info->pcie_base + DPMAIF_DL_BAT_INIT,
529 if (ret) {
531 return ret;
536 ret = ioread32_poll_timeout_atomic(hw_info->pcie_base + DPMAIF_DL_BAT_INIT,
539 if (ret)
542 return ret;
816 int ret;
841 ret = t7xx_dpmaif_dl_bat_init_done(hw_info, true);
842 if (ret)
843 return ret;
849 ret = t7xx_dpmaif_dl_bat_init_done(hw_info, false);
850 if (ret)
851 return ret;
930 int ret;
936 ret = ioread32_poll_timeout_atomic(hw_info->pcie_base + DPMAIF_AP_OVERWRITE_CFG,
939 if (ret)
940 return ret;
1010 int ret;
1015 ret = ioread32_poll_timeout_atomic(hw_info->pcie_base + DPMAIF_DL_DLQPIT_ADD,
1018 if (ret) {
1020 return ret;
1025 ret = ioread32_poll_timeout_atomic(hw_info->pcie_base + DPMAIF_DL_DLQPIT_ADD,
1028 if (ret) {
1030 return ret;
1236 int ret;
1238 ret = t7xx_dpmaif_hw_config(hw_info);
1239 if (ret) {
1241 return ret;
1244 ret = t7xx_dpmaif_init_intr(hw_info);
1245 if (ret) {
1247 return ret;
1254 ret = t7xx_dpmaif_config_dlq_hw(hw_info);
1255 if (ret) {
1257 return ret;
1262 ret = t7xx_dpmaif_hw_init_done(hw_info);
1263 if (ret)
1266 return ret;