Lines Matching refs:rtwdev
169 static void rtw8852c_ctrl_btg(struct rtw89_dev *rtwdev, bool btg);
170 static void rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev, u8 tx_path,
173 static int rtw8852c_pwr_on_func(struct rtw89_dev *rtwdev)
178 val32 = rtw89_read32_mask(rtwdev, R_AX_SYS_STATUS1, B_AX_PAD_HCI_SEL_V2_MASK);
180 rtw89_write32_set(rtwdev, R_AX_LDO_AON_CTRL0, B_AX_PD_REGU_L);
182 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN |
184 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC);
185 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC);
186 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN);
187 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
190 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
194 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
195 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC);
198 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
202 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
203 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
204 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
205 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
207 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
208 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1);
210 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_CMAC1_FEN);
211 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_R_SYM_ISO_CMAC12PP);
212 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, B_AX_R_SYM_WLCMAC1_P4_PC_EN |
217 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3);
219 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL,
224 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3);
226 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL,
230 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI,
234 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI,
238 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF);
241 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI,
245 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI,
249 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC);
252 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS);
255 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP);
259 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
260 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE);
261 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15);
265 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14);
266 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
267 rtw89_write32_set(rtwdev, R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN,
271 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,
279 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN,
285 rtw89_write32_mask(rtwdev, R_AX_LED1_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_V1_MASK,
291 static int rtw8852c_pwr_off_func(struct rtw89_dev *rtwdev)
296 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF,
300 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI);
303 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI);
306 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00);
309 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, XTAL_SI_RF10);
312 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC,
316 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI);
319 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI);
323 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
324 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB);
325 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
327 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3);
329 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SHDN_WL);
333 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3);
335 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_GND_SHDN_WL);
339 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC);
342 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
346 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, 0x0001A0B0);
347 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_XTAL_OFF_A_DIE);
348 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
361 static void rtw8852c_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
364 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
377 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
389 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
405 static void rtw8852c_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev,
408 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
430 static int rtw8852c_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map)
432 struct rtw89_efuse *efuse = &rtwdev->efuse;
439 rtw8852c_efuse_parsing_tssi(rtwdev, map);
440 rtw8852c_efuse_parsing_gain_offset(rtwdev, map);
442 switch (rtwdev->hci.type) {
450 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
455 static void rtw8852c_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
457 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
460 u32 addr = rtwdev->chip->phycap_addr;
488 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
494 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
500 static void rtw8852c_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
503 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
505 u32 addr = rtwdev->chip->phycap_addr;
511 rtw89_debug(rtwdev, RTW89_DBG_RFK,
520 static void rtw8852c_thermal_trim(struct rtw89_dev *rtwdev)
527 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
531 rtw89_debug(rtwdev, RTW89_DBG_RFK,
539 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val);
541 rtw89_debug(rtwdev, RTW89_DBG_RFK,
548 static void rtw8852c_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
551 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
553 u32 addr = rtwdev->chip->phycap_addr;
559 rtw89_debug(rtwdev, RTW89_DBG_RFK,
568 static void rtw8852c_pa_bias_trim(struct rtw89_dev *rtwdev)
570 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
575 rtw89_debug(rtwdev, RTW89_DBG_RFK,
585 rtw89_debug(rtwdev, RTW89_DBG_RFK,
589 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g);
590 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g);
594 static int rtw8852c_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
596 rtw8852c_phycap_parsing_tssi(rtwdev, phycap_map);
597 rtw8852c_phycap_parsing_thermal_trim(rtwdev, phycap_map);
598 rtw8852c_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
603 static void rtw8852c_power_trim(struct rtw89_dev *rtwdev)
605 rtw8852c_thermal_trim(rtwdev);
606 rtw8852c_pa_bias_trim(rtwdev);
609 static void rtw8852c_set_channel_mac(struct rtw89_dev *rtwdev,
613 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx);
614 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx);
615 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx);
622 txsc80 = rtw89_phy_get_txsc(rtwdev, chan,
626 txsc40 = rtw89_phy_get_txsc(rtwdev, chan,
630 txsc20 = rtw89_phy_get_txsc(rtwdev, chan,
659 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, rf_mod_val);
660 rtw89_write32(rtwdev, sub_carr, txsc);
671 rtw89_warn(rtwdev, "Invalid band_type:%d\n", chan->band_type);
674 rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE | B_AX_CHECK_CCK_EN |
676 rtw89_write8_set(rtwdev, chk_rate, chk_rate_mask);
689 static int rtw8852c_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch,
702 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw);
705 rtw89_phy_write32_mask(rtwdev, R_BK_FC0_INV_V1, B_BK_FC0_INV_MSK_V1,
707 rtw89_phy_write32_mask(rtwdev, R_CCK_FC0_INV_V1, B_CCK_FC0_INV_MSK_V1,
799 static void rtw8852c_set_gain_error(struct rtw89_dev *rtwdev,
803 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain;
818 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
829 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
835 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
840 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
848 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
859 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
863 static void rtw8852c_set_gain_offset(struct rtw89_dev *rtwdev,
872 struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain;
880 if (rtwdev->dbcc_en && path == RF_PATH_B)
889 rtw89_phy_write32_mask(rtwdev, R_RPL_OFST, B_RPL_OFST_MASK, tmp & 0x7f);
899 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[path], B_PATH0_R_G_OFST_MASK, tmp & 0xff);
902 rtw89_phy_write32_idx(rtwdev, R_RPL_PATHAB, rpl_mask[path], tmp & 0xff, phy_idx);
903 rtw89_phy_write32_idx(rtwdev, R_RSSI_M_PATHAB, rpl_tb_mask[path], tmp & 0xff, phy_idx);
906 static void rtw8852c_ctrl_ch(struct rtw89_dev *rtwdev,
919 rtw89_warn(rtwdev, "Invalid central_freq\n");
925 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_A);
926 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_A);
929 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
933 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
937 if (!rtwdev->dbcc_en) {
938 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_B);
939 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_B);
942 rtw89_phy_write32_idx(rtwdev,
947 rtw89_phy_write32_idx(rtwdev,
951 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL);
954 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL);
956 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL);
959 rtw89_phy_write32_idx(rtwdev, R_FC0_V1, B_FC0_MSK_V1,
963 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, sco,
967 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_B);
968 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_B);
971 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1,
975 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1,
979 rtw89_phy_write32_idx(rtwdev, R_FC0_V1, B_FC0_MSK_V1,
983 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, sco,
989 rtw89_phy_write32_mask(rtwdev, R_PCOEFF0_V1,
991 rtw89_phy_write32_mask(rtwdev, R_PCOEFF2_V1,
993 rtw89_phy_write32_mask(rtwdev, R_PCOEFF4_V1,
995 rtw89_phy_write32_mask(rtwdev, R_PCOEFF6_V1,
997 rtw89_phy_write32_mask(rtwdev, R_PCOEFF8_V1,
999 rtw89_phy_write32_mask(rtwdev, R_PCOEFFA_V1,
1001 rtw89_phy_write32_mask(rtwdev, R_PCOEFFC_V1,
1003 rtw89_phy_write32_mask(rtwdev, R_PCOEFFE_V1,
1006 rtw89_phy_write32_mask(rtwdev, R_PCOEFF0_V1,
1008 rtw89_phy_write32_mask(rtwdev, R_PCOEFF2_V1,
1010 rtw89_phy_write32_mask(rtwdev, R_PCOEFF4_V1,
1012 rtw89_phy_write32_mask(rtwdev, R_PCOEFF6_V1,
1014 rtw89_phy_write32_mask(rtwdev, R_PCOEFF8_V1,
1016 rtw89_phy_write32_mask(rtwdev, R_PCOEFFA_V1,
1018 rtw89_phy_write32_mask(rtwdev, R_PCOEFFC_V1,
1020 rtw89_phy_write32_mask(rtwdev, R_PCOEFFE_V1,
1025 chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band);
1026 rtw89_phy_write32_idx(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx, phy_idx);
1029 static void rtw8852c_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path)
1036 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1);
1037 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0);
1040 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2);
1041 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1);
1047 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
1048 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
1051 rtw89_warn(rtwdev, "Fail to set ADC\n");
1055 static void rtw8852c_edcca_per20_bitmap_sifs(struct rtw89_dev *rtwdev, u8 bw,
1059 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A1, B_SNDCCA_A1_EN, 0xff, phy_idx);
1060 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A2, B_SNDCCA_A2_VAL, 0, phy_idx);
1062 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A1, B_SNDCCA_A1_EN, 0, phy_idx);
1063 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A2, B_SNDCCA_A2_VAL, 0, phy_idx);
1068 rtw8852c_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw,
1083 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0,
1085 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW,
1087 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 0x0,
1089 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1,
1091 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1,
1093 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1,
1095 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1,
1099 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1,
1101 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
1103 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1106 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1,
1108 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1,
1110 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1,
1112 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1,
1116 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2,
1118 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
1120 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1123 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1,
1125 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1,
1127 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1,
1129 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1,
1133 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x3,
1135 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0,
1137 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH,
1140 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1,
1142 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1,
1144 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1,
1146 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1,
1150 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw,
1155 rtw89_phy_write32_idx(rtwdev, R_RX_BW40_2XFFT_EN_V1,
1157 rtw89_phy_write32_idx(rtwdev, R_T2F_GI_COMB, B_T2F_GI_COMB_EN, 1, phy_idx);
1159 rtw89_phy_write32_idx(rtwdev, R_RX_BW40_2XFFT_EN_V1,
1161 rtw89_phy_write32_idx(rtwdev, R_T2F_GI_COMB, B_T2F_GI_COMB_EN, 0, phy_idx);
1165 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_A);
1166 if (!rtwdev->dbcc_en)
1167 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_B);
1169 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_B);
1172 rtw8852c_edcca_per20_bitmap_sifs(rtwdev, bw, phy_idx);
1175 static u32 rtw8852c_spur_freq(struct rtw89_dev *rtwdev,
1214 static void rtw8852c_set_csi_tone_idx(struct rtw89_dev *rtwdev,
1221 spur_freq = rtw8852c_spur_freq(rtwdev, chan);
1223 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 0, phy_idx);
1231 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, csi_tone_idx, phy_idx);
1232 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1, phy_idx);
1254 static void rtw8852c_set_nbi_tone_idx(struct rtw89_dev *rtwdev,
1265 spur_freq = rtw8852c_spur_freq(rtwdev, chan);
1267 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0);
1268 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0);
1296 rtw89_phy_write32_mask(rtwdev, nbi->notch2_idx.addr,
1298 rtw89_phy_write32_mask(rtwdev, nbi->notch2_frac_idx.addr,
1300 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 0);
1301 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 1);
1302 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0);
1304 rtw89_phy_write32_mask(rtwdev, nbi->notch1_idx.addr,
1306 rtw89_phy_write32_mask(rtwdev, nbi->notch1_frac_idx.addr,
1308 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0);
1309 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 1);
1310 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 0);
1314 static void rtw8852c_spur_notch(struct rtw89_dev *rtwdev, u32 val,
1328 rtw89_phy_write32_mask(rtwdev, notch,
1330 rtw89_phy_write32_set(rtwdev, notch, B_PATH0_NOTCH_EN);
1331 rtw89_phy_write32_mask(rtwdev, notch2,
1333 rtw89_phy_write32_set(rtwdev, notch2, B_PATH0_NOTCH2_EN);
1336 static void rtw8852c_spur_elimination(struct rtw89_dev *rtwdev,
1341 rtw8852c_set_csi_tone_idx(rtwdev, chan, phy_idx);
1347 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_0);
1348 if (!rtwdev->dbcc_en)
1349 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_1);
1353 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_0);
1354 if (!rtwdev->dbcc_en)
1355 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_1);
1357 rtw8852c_set_nbi_tone_idx(rtwdev, chan, RF_PATH_A);
1358 if (!rtwdev->dbcc_en)
1359 rtw8852c_set_nbi_tone_idx(rtwdev, chan,
1366 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_1);
1370 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_1);
1372 rtw8852c_set_nbi_tone_idx(rtwdev, chan, RF_PATH_B);
1377 rtw89_phy_write32_idx(rtwdev, R_PD_BOOST_EN, B_PD_BOOST_EN, 0, phy_idx);
1379 rtw89_phy_write32_idx(rtwdev, R_PD_BOOST_EN, B_PD_BOOST_EN, 1, phy_idx);
1382 static void rtw8852c_5m_mask(struct rtw89_dev *rtwdev,
1407 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x0);
1408 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x0);
1409 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT,
1413 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_TH, 0x4);
1414 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x1);
1415 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB2, 0x0);
1416 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB0, 0x1);
1417 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_TH, 0x4);
1418 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x1);
1419 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB2, 0x0);
1420 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB0, 0x1);
1422 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_TH, 0x4);
1423 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x1);
1424 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB2, 0x1);
1425 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB0, 0x0);
1426 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_TH, 0x4);
1427 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x1);
1428 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB2, 0x1);
1429 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB0, 0x0);
1431 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT, B_ASSIGN_SBD_OPT_EN, 0x1, phy_idx);
1435 static void rtw8852c_bb_reset_all(struct rtw89_dev *rtwdev,
1439 rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG,
1441 rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG,
1446 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
1448 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0,
1451 rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG,
1453 rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG,
1456 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
1460 static void rtw8852c_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band,
1464 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
1466 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS,
1468 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1,
1471 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x0);
1472 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0);
1474 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x1);
1475 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1);
1476 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
1478 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS,
1481 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0,
1486 static void rtw8852c_bb_reset(struct rtw89_dev *rtwdev,
1489 rtw8852c_bb_reset_all(rtwdev, phy_idx);
1493 void rtw8852c_bb_gpio_trsw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
1510 rtw89_phy_write32_mask(rtwdev, cr, (B_P0_TRSW_A | B_P0_TRSW_B) << mask_ofst, val);
1520 void rtw8852c_bb_gpio_rfm(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
1542 rtw89_phy_write32_mask(rtwdev, cr, mask, val);
1545 static void rtw8852c_bb_gpio_init(struct rtw89_dev *rtwdev)
1553 rtw89_phy_write32_set(rtwdev, (addr | 0x68), B_P0_TRSW_A);
1554 rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_X);
1555 rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_SO_A2);
1556 rtw89_phy_write32(rtwdev, (addr | 0x80), 0x77777777);
1557 rtw89_phy_write32(rtwdev, (addr | 0x84), 0x77777777);
1560 rtw89_phy_write32(rtwdev, R_RFE_E_A2, 0xffffffff);
1561 rtw89_phy_write32(rtwdev, R_RFE_O_SEL_A2, 0);
1562 rtw89_phy_write32(rtwdev, R_RFE_SEL0_A2, 0);
1563 rtw89_phy_write32(rtwdev, R_RFE_SEL32_A2, 0);
1565 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 0, 0, 1);
1566 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 1, 1, 0);
1567 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 0, 1, 0);
1568 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 1, 1, 0);
1569 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 0, 0, 1);
1570 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 1, 1, 0);
1571 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 0, 1, 0);
1572 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 1, 1, 0);
1574 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 0, 0, 1);
1575 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 1, 1, 0);
1576 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 0, 1, 0);
1577 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 1, 1, 0);
1578 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 0, 0, 1);
1579 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 1, 1, 0);
1580 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 0, 1, 0);
1581 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 1, 1, 0);
1583 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, PAPE_RFM, 0, 0, 0, 0x0);
1584 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, TRSW_RFM, 0, 0, 0, 0x4);
1585 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, LNAON_RFM, 0, 0, 0, 0x8);
1587 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, PAPE_RFM, 0, 0, 0, 0x0);
1588 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, TRSW_RFM, 0, 0, 0, 0x4);
1589 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, LNAON_RFM, 0, 0, 0, 0x8);
1592 static void rtw8852c_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,
1599 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
1602 static void rtw8852c_bb_sethw(struct rtw89_dev *rtwdev)
1604 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1606 rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT,
1608 rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT2,
1611 rtw8852c_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0);
1612 rtw8852c_bb_gpio_init(rtwdev);
1616 rtw89_phy_read32_mask(rtwdev, R_RPL_BIAS_COMP, B_RPL_BIAS_COMP_MASK);
1618 rtw89_phy_read32_mask(rtwdev, R_RPL_BIAS_COMP1, B_RPL_BIAS_COMP1_MASK);
1621 static void rtw8852c_set_channel_bb(struct rtw89_dev *rtwdev,
1627 struct rtw89_hal *hal = &rtwdev->hal;
1634 rtw8852c_ctrl_sco_cck(rtwdev, chan->channel,
1638 rtw8852c_ctrl_ch(rtwdev, chan, phy_idx);
1639 rtw8852c_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx);
1641 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1);
1642 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0);
1643 rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF,
1646 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0);
1647 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 1);
1648 rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF,
1652 rtw8852c_spur_elimination(rtwdev, chan, pri_ch_idx, phy_idx);
1653 rtw8852c_ctrl_btg(rtwdev, chan->band_type == RTW89_BAND_2G);
1654 rtw8852c_5m_mask(rtwdev, chan, phy_idx);
1657 rtwdev->hal.cv != CHIP_CAV) {
1658 rtw89_phy_write32_idx(rtwdev, R_P80_AT_HIGH_FREQ,
1660 reg = rtw89_mac_reg_by_idx(rtwdev, R_P80_AT_HIGH_FREQ_BB_WRP, phy_idx);
1662 rtw89_phy_write32_mask(rtwdev,
1665 rtw89_write32_mask(rtwdev, reg,
1668 rtw89_phy_write32_mask(rtwdev,
1671 rtw89_write32_mask(rtwdev, reg,
1678 rtw89_phy_write32_idx(rtwdev, R_CDD_EVM_CHK_EN,
1681 rtw89_phy_write32_idx(rtwdev, R_CDD_EVM_CHK_EN,
1684 if (!rtwdev->dbcc_en) {
1686 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1);
1687 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3);
1689 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1);
1690 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3);
1694 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1);
1695 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3);
1698 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1);
1699 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3);
1704 rtw89_phy_write32_set(rtwdev, R_MUIC, B_MUIC_EN);
1706 rtw89_phy_write32_clr(rtwdev, R_MUIC, B_MUIC_EN);
1713 rtw8852c_ctrl_tx_path_tmac(rtwdev, ntx_path, (enum rtw89_mac_idx)phy_idx);
1715 rtw8852c_bb_reset_all(rtwdev, phy_idx);
1718 static void rtw8852c_set_channel(struct rtw89_dev *rtwdev,
1723 rtw8852c_set_channel_mac(rtwdev, chan, mac_idx);
1724 rtw8852c_set_channel_bb(rtwdev, chan, phy_idx);
1725 rtw8852c_set_channel_rf(rtwdev, chan, phy_idx);
1728 static void rtw8852c_dfs_en(struct rtw89_dev *rtwdev, bool en)
1731 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1);
1733 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0);
1736 static void rtw8852c_adc_en(struct rtw89_dev *rtwdev, bool en)
1739 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST,
1742 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST,
1746 static void rtw8852c_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
1753 rtw89_chip_stop_sch_tx(rtwdev, mac_idx, &p->tx_en,
1755 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false);
1756 rtw8852c_dfs_en(rtwdev, false);
1757 rtw8852c_tssi_cont_en_phyidx(rtwdev, false, phy_idx);
1758 rtw8852c_adc_en(rtwdev, false);
1760 rtw8852c_bb_reset_en(rtwdev, chan->band_type, phy_idx, false);
1762 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true);
1763 rtw8852c_adc_en(rtwdev, true);
1764 rtw8852c_dfs_en(rtwdev, true);
1765 rtw8852c_tssi_cont_en_phyidx(rtwdev, true, phy_idx);
1766 rtw8852c_bb_reset_en(rtwdev, chan->band_type, phy_idx, true);
1767 rtw89_chip_resume_sch_tx(rtwdev, mac_idx, p->tx_en);
1771 static void rtw8852c_rfk_init(struct rtw89_dev *rtwdev)
1773 struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc;
1775 rtwdev->is_tssi_mode[RF_PATH_A] = false;
1776 rtwdev->is_tssi_mode[RF_PATH_B] = false;
1778 rtw8852c_lck_init(rtwdev);
1780 rtw8852c_rck(rtwdev);
1781 rtw8852c_dack(rtwdev);
1782 rtw8852c_rx_dck(rtwdev, RTW89_PHY_0, false);
1785 static void rtw8852c_rfk_channel(struct rtw89_dev *rtwdev)
1789 rtw8852c_mcc_get_ch_info(rtwdev, phy_idx);
1790 rtw8852c_rx_dck(rtwdev, phy_idx, false);
1791 rtw8852c_iqk(rtwdev, phy_idx);
1792 rtw8852c_tssi(rtwdev, phy_idx);
1793 rtw8852c_dpk(rtwdev, phy_idx);
1794 rtw89_fw_h2c_rf_ntfy_mcc(rtwdev);
1797 static void rtw8852c_rfk_band_changed(struct rtw89_dev *rtwdev,
1800 rtw8852c_tssi_scan(rtwdev, phy_idx);
1803 static void rtw8852c_rfk_scan(struct rtw89_dev *rtwdev, bool start)
1805 rtw8852c_wifi_scan_notify(rtwdev, start, RTW89_PHY_0);
1808 static void rtw8852c_rfk_track(struct rtw89_dev *rtwdev)
1810 rtw8852c_dpk_track(rtwdev);
1811 rtw8852c_lck_track(rtwdev);
1812 rtw8852c_rx_dck_track(rtwdev);
1815 static u32 rtw8852c_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,
1834 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1842 void rtw8852c_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
1852 rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst);
1859 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_1tx=0x%x\n", val_1t);
1860 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_2tx=0x%x\n", val_2t);
1864 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx);
1865 rtw89_write32_mask(rtwdev, reg,
1869 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx);
1870 rtw89_write32_mask(rtwdev, reg,
1876 static void rtw8852c_set_txpwr_ref(struct rtw89_dev *rtwdev,
1888 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n");
1890 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL,
1893 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n");
1894 val = rtw8852c_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm);
1897 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val,
1900 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n");
1901 val = rtw8852c_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck);
1904 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val,
1908 static void rtw8852c_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev,
1938 rtw89_warn(rtwdev,
1949 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1952 rtw89_phy_write32_idx(rtwdev, addr_filter[i], __DFIR_CFG_MASK,
1963 static void rtw8852c_set_tx_shape(struct rtw89_dev *rtwdev,
1968 u8 regd = rtw89_regd_get(rtwdev, band);
1973 rtw8852c_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_cck, phy_idx);
1975 rtw89_phy_tssi_ctrl_set_bandedge_cfg(rtwdev,
1980 static void rtw8852c_set_txpwr(struct rtw89_dev *rtwdev,
1984 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
1985 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
1986 rtw8852c_set_tx_shape(rtwdev, chan, phy_idx);
1987 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
1988 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
1991 static void rtw8852c_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
1994 rtw8852c_set_txpwr_ref(rtwdev, phy_idx);
1998 rtw8852c_init_tssi_ctrl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
2012 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
2015 rtw89_mac_txpwr_write32(rtwdev, phy_idx, ctrl_ini[i].addr,
2018 rtw89_phy_tssi_ctrl_set_bandedge_cfg(rtwdev,
2024 rtw8852c_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
2028 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333);
2032 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000);
2036 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff);
2040 rtw8852c_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ?
2043 rtw8852c_init_tssi_ctrl(rtwdev, phy_idx);
2048 static void rtw8852c_bb_cfg_rx_path(struct rtw89_dev *rtwdev, u8 rx_path)
2050 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
2055 if (rtwdev->dbcc_en) {
2056 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_ANT_RX_SEG0, 1);
2057 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_ANT_RX_SEG0, 2,
2060 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG0,
2062 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG1,
2064 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG0, 2,
2066 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG1, 2,
2069 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT,
2071 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT,
2073 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 8);
2074 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
2075 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
2077 rtw89_phy_write32_idx(rtwdev, R_RXHT_MCS_LIMIT,
2079 rtw89_phy_write32_idx(rtwdev, R_RXVHT_MCS_LIMIT,
2081 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHE_USER_MAX, 1,
2083 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0,
2085 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0,
2087 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1);
2088 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3);
2089 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1);
2090 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3);
2093 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD,
2095 rtw89_phy_write32_mask(rtwdev, R_FC0_BW,
2097 rtw89_phy_write32_mask(rtwdev, R_FC0_BW,
2099 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT,
2101 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT,
2103 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS,
2105 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS,
2107 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
2109 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
2112 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD,
2114 rtw89_phy_write32_mask(rtwdev, R_FC0_BW,
2116 rtw89_phy_write32_mask(rtwdev, R_FC0_BW,
2118 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT,
2120 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT,
2122 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS,
2124 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS,
2126 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB,
2128 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB,
2131 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD,
2133 rtw89_phy_write32_mask(rtwdev, R_FC0_BW,
2135 rtw89_phy_write32_mask(rtwdev, R_FC0_BW,
2137 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT,
2139 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT,
2141 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS,
2143 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS,
2145 rtw8852c_ctrl_btg(rtwdev, band == RTW89_BAND_2G);
2146 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
2148 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
2150 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB,
2152 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB,
2155 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 8);
2159 static void rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev, u8 tx_path,
2181 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, RTW89_PHY_0);
2182 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, RTW89_PHY_1);
2186 reg = rtw89_mac_reg_by_idx(rtwdev, addr, mac_idx);
2187 rtw89_write32(rtwdev, reg, 0);
2209 rtw89_warn(rtwdev, "[Invalid Tx Path]Tx Path: %d\n", tx_path);
2214 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "0x%x = 0x%x\n",
2216 reg = rtw89_mac_reg_by_idx(rtwdev, path_com[i].addr, mac_idx);
2217 rtw89_write32(rtwdev, reg, path_com[i].data);
2221 static void rtw8852c_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, bool bt_en)
2224 rtw89_phy_write32_mask(rtwdev, R_PATH0_FRC_FIR_TYPE_V1,
2226 rtw89_phy_write32_mask(rtwdev, R_PATH1_FRC_FIR_TYPE_V1,
2228 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXBB_V1,
2230 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXBB_V1,
2232 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
2234 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1,
2236 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
2238 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA1_LNA6_OP1DB_V1,
2240 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1,
2242 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA1_LNA6_OP1DB_V1,
2244 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_BACKOFF_V1,
2246 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_BACKOFF_V1,
2248 rtw89_phy_write32_mask(rtwdev, R_P0_BACKOFF_IBADC_V1,
2250 rtw89_phy_write32_mask(rtwdev, R_P1_BACKOFF_IBADC_V1,
2253 rtw89_phy_write32_mask(rtwdev, R_PATH0_FRC_FIR_TYPE_V1,
2255 rtw89_phy_write32_mask(rtwdev, R_PATH1_FRC_FIR_TYPE_V1,
2257 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXBB_V1,
2259 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXBB_V1,
2261 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
2263 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1,
2265 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
2267 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA1_LNA6_OP1DB_V1,
2269 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1,
2271 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA1_LNA6_OP1DB_V1,
2273 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_BACKOFF_V1,
2275 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_BACKOFF_V1,
2277 rtw89_phy_write32_mask(rtwdev, R_P0_BACKOFF_IBADC_V1,
2279 rtw89_phy_write32_mask(rtwdev, R_P1_BACKOFF_IBADC_V1,
2284 static void rtw8852c_bb_cfg_txrx_path(struct rtw89_dev *rtwdev)
2286 struct rtw89_hal *hal = &rtwdev->hal;
2288 rtw8852c_bb_cfg_rx_path(rtwdev, RF_PATH_AB);
2291 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
2292 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
2293 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
2294 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
2296 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1);
2297 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1);
2298 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1);
2299 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1);
2303 static u8 rtw8852c_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
2305 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
2306 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0);
2307 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
2311 return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
2314 static void rtw8852c_btc_set_rfe(struct rtw89_dev *rtwdev)
2316 struct rtw89_btc *btc = &rtwdev->btc;
2319 module->rfe_type = rtwdev->efuse.rfe_type;
2320 module->cv = rtwdev->hal.cv;
2341 static void rtw8852c_ctrl_btg(struct rtw89_dev *rtwdev, bool btg)
2344 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
2346 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
2348 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1,
2350 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1,
2352 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1,
2354 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1,
2356 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0);
2357 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_BT_SHARE, 0x1);
2358 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_BT_SEG0, 0x2);
2359 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN,
2361 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN,
2364 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
2366 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
2368 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1,
2370 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1,
2372 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1,
2374 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1,
2376 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf);
2377 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4);
2378 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_BT_SHARE, 0x0);
2379 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_BT_SEG0, 0x0);
2380 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN,
2382 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN,
2388 void rtw8852c_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
2390 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x20000);
2391 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group);
2392 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val);
2393 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0);
2396 static void rtw8852c_btc_init_cfg(struct rtw89_dev *rtwdev)
2398 struct rtw89_btc *btc = &rtwdev->btc;
2400 const struct rtw89_chip_info *chip = rtwdev->chip;
2407 rtw89_mac_coex_init_v1(rtwdev, &coex_params);
2410 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true);
2411 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true);
2414 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, RFREG_MASK, 0x0);
2415 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, RFREG_MASK, 0x0);
2419 rtw8852c_set_trx_mask(rtwdev,
2421 rtw8852c_set_trx_mask(rtwdev,
2424 rtw8852c_set_trx_mask(rtwdev,
2427 rtw8852c_set_trx_mask(rtwdev,
2429 rtw8852c_set_trx_mask(rtwdev,
2434 rtw89_write32(rtwdev, R_AX_BT_BREAK_TABLE, BTC_BREAK_PARAM);
2437 rtw89_write32_set(rtwdev,
2444 void rtw8852c_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)
2463 rtw89_write32_set(rtwdev, reg, bitmap);
2465 rtw89_write32_clr(rtwdev, reg, bitmap);
2490 rtw8852c_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
2503 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \
2536 s8 rtw8852c_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
2588 void rtw8852c_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
2594 void rtw8852c_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
2596 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000);
2597 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
2598 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x620);
2602 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0,
2605 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0,
2608 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
2611 static void rtw8852c_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level)
2620 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000);
2621 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0);
2622 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
2623 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
2624 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17);
2625 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2);
2626 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
2627 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3);
2628 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17);
2629 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
2632 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000);
2633 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0);
2634 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
2635 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
2636 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5);
2637 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2);
2638 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15);
2639 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3);
2640 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5);
2641 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
2646 static void rtw8852c_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
2648 struct rtw89_btc *btc = &rtwdev->btc;
2653 rtw8852c_bb_ctrl_btc_preagc(rtwdev, false);
2657 rtw8852c_bb_ctrl_btc_preagc(rtwdev, true);
2661 rtw8852c_bb_ctrl_btc_preagc(rtwdev, false);
2666 rtw8852c_set_wl_lna2(rtwdev, btc->dm.wl_lna2);
2669 static void rtw8852c_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
2680 rtw89_decode_chan_idx(rtwdev, chan_idx, &ch, &band);
2685 static void rtw8852c_query_ppdu(struct rtw89_dev *rtwdev,
2693 for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
2698 rtw8852c_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
2701 static int rtw8852c_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
2705 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN,
2708 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2709 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2710 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2712 rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S0_LDO_VSEL_F_MASK, 0x1);
2713 rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S1_LDO_VSEL_F_MASK, 0x1);
2715 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL0, 0x7, FULL_BIT_MASK);
2719 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x6c, FULL_BIT_MASK);
2723 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xc7, FULL_BIT_MASK);
2727 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xc7, FULL_BIT_MASK);
2731 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL3, 0xd, FULL_BIT_MASK);
2738 static int rtw8852c_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
2740 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN,