Lines Matching defs:path
378 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
390 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
495 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n",
512 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n",
542 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n",
560 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
586 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
801 enum rtw89_rf_path path)
812 reg = bb_gain_lna[i].gain_g[path];
814 reg = bb_gain_lna[i].gain_a[path];
817 val = gain->lna_gain[gain_band][path][i];
821 reg = bb_gain_bypass_lna[i].gain_g[path];
824 reg = bb_gain_bypass_lna[i].gain_a[path];
828 val = gain->lna_gain_bypass[gain_band][path][i];
832 reg = bb_gain_op1db_a.reg[i].lna[path];
834 val = gain->lna_op1db[gain_band][path][i];
837 reg = bb_gain_op1db_a.reg[i].tia_lna[path];
839 val = gain->tia_lna_op1db[gain_band][path][i];
845 reg = bb_gain_op1db_a.reg_tia0_lna6[path];
847 val = gain->tia_lna_op1db[gain_band][path][7];
853 reg = bb_gain_tia[i].gain_g[path];
855 reg = bb_gain_tia[i].gain_a[path];
858 val = gain->tia_gain[gain_band][path][i];
866 enum rtw89_rf_path path)
880 if (rtwdev->dbcc_en && path == RF_PATH_B)
884 offset_q0 = efuse_gain->offset[path][RTW89_GAIN_OFFSET_2G_CCK];
894 offset_q0 = -efuse_gain->offset[path][gain_band];
899 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[path], B_PATH0_R_G_OFST_MASK, tmp & 0xff);
902 rtw89_phy_write32_idx(rtwdev, R_RPL_PATHAB, rpl_mask[path], tmp & 0xff, phy_idx);
903 rtw89_phy_write32_idx(rtwdev, R_RSSI_M_PATHAB, rpl_tb_mask[path], tmp & 0xff, phy_idx);
1029 static void rtw8852c_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path)
1036 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1);
1037 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0);
1040 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2);
1041 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1);
1047 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
1048 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
1256 enum rtw89_rf_path path)
1258 const struct rtw89_nbi_reg_def *nbi = &rtw8852c_nbi_reg_def[path];
1493 void rtw8852c_bb_gpio_trsw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
1502 if (path >= ARRAY_SIZE(path_cr_bases))
1505 cr = path_cr_bases[path];
1520 void rtw8852c_bb_gpio_rfm(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
1530 if (src >= ARRAY_SIZE(masks) || path >= ARRAY_SIZE(path_cr_bases))
1534 cr = path_cr_bases[path];
2388 void rtw8852c_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
2390 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x20000);
2391 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group);
2392 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val);
2393 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0);
2423 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */
2689 u8 path;
2693 for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
2694 status->chains |= BIT(path);
2695 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]);