Lines Matching refs:rtwdev
254 static int rtw8851b_pwr_on_func(struct rtw89_dev *rtwdev)
260 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN |
262 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC);
263 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC);
264 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN);
265 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
268 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
272 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
273 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC);
276 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
280 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
281 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
282 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
283 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
285 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
286 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1);
288 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI,
292 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI,
296 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF);
299 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI,
303 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI,
307 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC);
310 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_SRAM_CTRL, 0, XTAL_SI_SRAM_DIS);
313 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS);
316 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP);
319 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_DRV, 0, XTAL_SI_DRV_LATCH);
323 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
324 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE);
325 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15);
329 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14);
330 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
331 rtw89_write32_set(rtwdev, R_AX_GPIO0_16_EECS_EESK_LED1_PULL_LOW_EN,
334 if (rtwdev->hal.cv == CHIP_CAV) {
335 ret = rtw89_read_efuse_ver(rtwdev, &val8);
337 rtwdev->hal.cv = val8;
340 rtw89_write32_clr(rtwdev, R_AX_WLAN_XTAL_SI_CONFIG,
342 if (rtwdev->hal.cv != CHIP_CAV) {
343 rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL1, B_AX_FPWMDELAY);
344 rtw89_write32_set(rtwdev, R_AX_SPSANA_ON_CTRL1, B_AX_FPWMDELAY);
347 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,
354 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN,
360 rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_MASK,
366 static void rtw8851b_patch_swr_pfm2pwm(struct rtw89_dev *rtwdev)
368 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_SOP_PWMM_DSWR);
369 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_SOP_ASWRM);
370 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_LPSOP_DSWRM);
371 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_LPSOP_ASWRM);
374 static int rtw8851b_pwr_off_func(struct rtw89_dev *rtwdev)
379 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF,
383 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI);
386 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI);
389 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00);
392 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC,
396 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI);
399 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI);
403 rtw89_write32_set(rtwdev, R_AX_WLAN_XTAL_SI_CONFIG,
405 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
406 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
407 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB);
409 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC);
412 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
416 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION);
418 if (rtwdev->hal.cv == CHIP_CAV) {
419 rtw8851b_patch_swr_pfm2pwm(rtwdev);
421 rtw89_write32_set(rtwdev, R_AX_SPSLDO_ON_CTRL1, B_AX_FPWMDELAY);
422 rtw89_write32_set(rtwdev, R_AX_SPSANA_ON_CTRL1, B_AX_FPWMDELAY);
425 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
438 static void rtw8851b_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
441 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
452 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
462 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
478 static void rtw8851b_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev,
481 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
503 static int rtw8851b_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map)
505 struct rtw89_efuse *efuse = &rtwdev->efuse;
512 rtw8851b_efuse_parsing_tssi(rtwdev, map);
513 rtw8851b_efuse_parsing_gain_offset(rtwdev, map);
515 switch (rtwdev->hci.type) {
523 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
528 static void rtw8851b_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
530 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
532 u32 addr = rtwdev->chip->phycap_addr;
550 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
556 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
562 static void rtw8851b_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
565 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
567 u32 addr = rtwdev->chip->phycap_addr;
573 rtw89_debug(rtwdev, RTW89_DBG_RFK,
582 static void rtw8851b_thermal_trim(struct rtw89_dev *rtwdev)
589 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
593 rtw89_debug(rtwdev, RTW89_DBG_RFK,
601 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val);
603 rtw89_debug(rtwdev, RTW89_DBG_RFK,
610 static void rtw8851b_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
613 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
615 u32 addr = rtwdev->chip->phycap_addr;
621 rtw89_debug(rtwdev, RTW89_DBG_RFK,
630 static void rtw8851b_pa_bias_trim(struct rtw89_dev *rtwdev)
632 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
637 rtw89_debug(rtwdev, RTW89_DBG_RFK,
647 rtw89_debug(rtwdev, RTW89_DBG_RFK,
651 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g);
652 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g);
656 static void rtw8851b_phycap_parsing_gain_comp(struct rtw89_dev *rtwdev, u8 *phycap_map)
661 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
662 u32 phycap_addr = rtwdev->chip->phycap_addr;
680 static int rtw8851b_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
682 rtw8851b_phycap_parsing_tssi(rtwdev, phycap_map);
683 rtw8851b_phycap_parsing_thermal_trim(rtwdev, phycap_map);
684 rtw8851b_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
685 rtw8851b_phycap_parsing_gain_comp(rtwdev, phycap_map);
690 static void rtw8851b_set_bb_gpio(struct rtw89_dev *rtwdev, u8 gpio_idx, bool inv,
702 rtw89_phy_write32_mask(rtwdev, addr, mask, RF_PATH_A);
703 rtw89_phy_write32_mask(rtwdev, R_RFE_INV0, BIT(gpio_idx), inv);
709 rtw89_phy_write32_mask(rtwdev, addr, mask, src_sel);
712 static void rtw8851b_set_mac_gpio(struct rtw89_dev *rtwdev, u8 func)
730 rtw89_warn(rtwdev, "undefined gpio func %d\n", func);
734 rtw89_write8_mask(rtwdev, def->addr, def->mask, def->data);
737 static void rtw8851b_rfe_gpio(struct rtw89_dev *rtwdev)
739 u8 rfe_type = rtwdev->efuse.rfe_type;
745 rtw8851b_set_bb_gpio(rtwdev, 16, true, RFE_SEL0_SRC_ANTSEL_0);
746 rtw8851b_set_bb_gpio(rtwdev, 17, false, RFE_SEL0_SRC_ANTSEL_0);
748 rtw8851b_set_mac_gpio(rtwdev, 16);
749 rtw8851b_set_mac_gpio(rtwdev, 17);
753 static void rtw8851b_power_trim(struct rtw89_dev *rtwdev)
755 rtw8851b_thermal_trim(rtwdev);
756 rtw8851b_pa_bias_trim(rtwdev);
759 static void rtw8851b_set_channel_mac(struct rtw89_dev *rtwdev,
763 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx);
764 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx);
765 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx);
770 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_40);
773 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_20);
781 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1));
782 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4));
785 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0));
786 rtw89_write32(rtwdev, sub_carr, txsc20);
789 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK);
790 rtw89_write32(rtwdev, sub_carr, 0);
797 rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE);
798 rtw89_write8_set(rtwdev, chk_rate,
801 rtw89_write8_set(rtwdev, chk_rate, B_AX_BAND_MODE);
802 rtw89_write8_clr(rtwdev, chk_rate,
817 static void rtw8851b_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 primary_ch)
821 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH,
823 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH,
885 static void rtw8851b_set_gain_error(struct rtw89_dev *rtwdev,
889 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain;
904 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
915 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
919 static void rtw8851b_set_gain_offset(struct rtw89_dev *rtwdev,
925 struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain;
938 rtw89_phy_write32_mask(rtwdev, gain_err_addr[path], MASKBYTE0, tmp);
951 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[RF_PATH_A], B_PATH0_R_G_OFST_MASK, tmp);
958 rtw89_phy_write32_idx(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx);
962 rtw89_phy_write32_idx(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx);
967 rtw89_phy_write32_mask(rtwdev, R_RX_RPL_OFST,
973 void rtw8851b_set_rxsc_rpl_comp(struct rtw89_dev *rtwdev, enum rtw89_subband subband)
975 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain;
983 rtw89_phy_write32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_MASK, val);
984 rtw89_phy_write32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_MASK, val);
990 rtw89_phy_write32(rtwdev, R_P0_RPL2, val);
991 rtw89_phy_write32(rtwdev, R_P1_RPL2, val);
997 rtw89_phy_write32(rtwdev, R_P0_RPL3, val);
998 rtw89_phy_write32(rtwdev, R_P1_RPL3, val);
1001 static void rtw8851b_ctrl_ch(struct rtw89_dev *rtwdev,
1011 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
1014 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
1018 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_INV, sco_comp, phy_idx);
1025 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3b13ff);
1026 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x1c42de);
1027 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfdb0ad);
1028 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xf60f6e);
1029 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xfd8f92);
1030 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011);
1031 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c);
1032 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xfff00a);
1034 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3d23ff);
1035 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x29b354);
1036 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8);
1037 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xfdb053);
1038 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xf86f9a);
1039 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0xfaef92);
1040 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0xfe5fcc);
1041 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xffdff5);
1044 rtw8851b_set_gain_error(rtwdev, subband, RF_PATH_A);
1045 rtw8851b_set_gain_offset(rtwdev, subband, phy_idx);
1046 rtw8851b_set_rxsc_rpl_comp(rtwdev, subband);
1049 static void rtw8851b_bw_setting(struct rtw89_dev *rtwdev, u8 bw)
1051 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_CTL, 0x8);
1052 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_EN, 0x2);
1053 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW0, B_P0_CFCH_BW0, 0x2);
1054 rtw89_phy_write32_mask(rtwdev, R_P0_CFCH_BW1, B_P0_CFCH_BW1, 0x4);
1055 rtw89_phy_write32_mask(rtwdev, R_DRCK, B_DRCK_MUL, 0xf);
1056 rtw89_phy_write32_mask(rtwdev, R_ADCMOD, B_ADCMOD_LP, 0xa);
1057 rtw89_phy_write32_mask(rtwdev, R_P0_RXCK, B_P0_RXCK_ADJ, 0x92);
1061 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x1);
1062 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x0);
1063 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x1);
1066 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x1);
1067 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x1);
1068 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
1071 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x2);
1072 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2);
1073 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
1076 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x2);
1077 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2);
1078 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
1081 rtw89_phy_write32_mask(rtwdev, R_DCIM, B_DCIM_FR, 0x0);
1082 rtw89_phy_write32_mask(rtwdev, R_WDADC, B_WDADC_SEL, 0x2);
1083 rtw89_phy_write32_mask(rtwdev, R_ADDCK0D, B_ADDCK_DS, 0x0);
1086 rtw89_warn(rtwdev, "Fail to set ADC\n");
1090 static void rtw8851b_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw,
1095 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
1096 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x1, phy_idx);
1097 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
1100 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
1101 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x2, phy_idx);
1102 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
1105 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
1106 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
1107 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
1110 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x1, phy_idx);
1111 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
1112 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH,
1116 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1);
1118 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0);
1122 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x2, phy_idx);
1123 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
1124 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH,
1128 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw,
1132 rtw8851b_bw_setting(rtwdev, bw);
1135 static void rtw8851b_ctrl_cck_en(struct rtw89_dev *rtwdev, bool cck_en)
1138 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0);
1139 rtw89_phy_write32_mask(rtwdev, R_PD_ARBITER_OFF,
1141 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1);
1143 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1);
1144 rtw89_phy_write32_mask(rtwdev, R_PD_ARBITER_OFF,
1146 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0);
1150 static u32 rtw8851b_spur_freq(struct rtw89_dev *rtwdev,
1174 static void rtw8851b_set_csi_tone_idx(struct rtw89_dev *rtwdev,
1181 spur_freq = rtw8851b_spur_freq(rtwdev, chan);
1183 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN_V1, B_SEG0CSI_EN,
1192 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_V1, B_SEG0CSI_IDX,
1194 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN_V1, B_SEG0CSI_EN, 1, phy_idx);
1206 static void rtw8851b_set_nbi_tone_idx(struct rtw89_dev *rtwdev,
1216 spur_freq = rtw8851b_spur_freq(rtwdev, chan);
1218 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1220 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1251 rtw89_phy_write32_mask(rtwdev, nbi->notch2_idx.addr,
1253 rtw89_phy_write32_mask(rtwdev, nbi->notch2_frac_idx.addr,
1255 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1257 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1259 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1262 rtw89_phy_write32_mask(rtwdev, nbi->notch1_idx.addr,
1264 rtw89_phy_write32_mask(rtwdev, nbi->notch1_frac_idx.addr,
1266 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1268 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr,
1270 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr,
1275 static void rtw8851b_set_cfr(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan)
1280 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
1282 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
1284 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
1286 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
1289 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
1291 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_CFR,
1293 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
1295 rtw89_phy_write32_mask(rtwdev, R_PATH0_TX_POLAR_CLIPPING,
1300 static void rtw8851b_5m_mask(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
1325 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x0);
1326 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1,
1332 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x5);
1333 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1);
1334 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x0);
1335 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x1);
1337 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x5);
1338 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1);
1339 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x1);
1340 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x0);
1342 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1,
1346 static void rtw8851b_bb_reset_all(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1348 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
1350 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1351 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
1352 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
1353 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1356 static void rtw8851b_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band,
1360 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
1362 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1364 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x0);
1365 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0);
1367 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x1);
1368 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1);
1369 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
1372 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
1376 static void rtw8851b_bb_reset(struct rtw89_dev *rtwdev,
1379 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
1381 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1382 rtw8851b_bb_reset_all(rtwdev, phy_idx);
1383 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB,
1385 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1389 void rtw8851b_bb_gpio_trsw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path,
1403 rtw89_phy_write32_mask(rtwdev, R_P0_TRSW,
1407 static void rtw8851b_bb_gpio_init(struct rtw89_dev *rtwdev)
1409 rtw89_phy_write32_set(rtwdev, R_P0_TRSW, B_P0_TRSW_A);
1410 rtw89_phy_write32_clr(rtwdev, R_P0_TRSW, B_P0_TRSW_X);
1411 rtw89_phy_write32_clr(rtwdev, R_P0_TRSW, B_P0_TRSW_SO_A2);
1412 rtw89_phy_write32(rtwdev, R_RFE_SEL0_BASE, 0x77777777);
1413 rtw89_phy_write32(rtwdev, R_RFE_SEL32_BASE, 0x77777777);
1415 rtw89_phy_write32(rtwdev, R_RFE_E_A2, 0xffffffff);
1416 rtw89_phy_write32(rtwdev, R_RFE_O_SEL_A2, 0);
1417 rtw89_phy_write32(rtwdev, R_RFE_SEL0_A2, 0);
1418 rtw89_phy_write32(rtwdev, R_RFE_SEL32_A2, 0);
1420 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 0, 0, 1);
1421 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 1, 1, 0);
1422 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 0, 1, 0);
1423 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 1, 1, 0);
1424 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 0, 0, 1);
1425 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 1, 1, 0);
1426 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 0, 1, 0);
1427 rtw8851b_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 1, 1, 0);
1430 static void rtw8851b_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,
1437 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
1440 static void rtw8851b_bb_sethw(struct rtw89_dev *rtwdev)
1442 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1444 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP);
1446 rtw8851b_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0);
1447 rtw8851b_bb_gpio_init(rtwdev);
1449 rtw89_write32_clr(rtwdev, R_AX_PWR_NORM_FORCE1, B_AX_FORCE_NTX_VALUE);
1450 rtw89_write32_set(rtwdev, R_AX_PWR_NORM_FORCE1, B_AX_FORCE_NTX_EN);
1454 rtw89_phy_read32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK);
1456 rtw89_phy_read32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK);
1459 static void rtw8851b_set_channel_bb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
1467 rtw8851b_ctrl_sco_cck(rtwdev, chan->primary_channel);
1469 rtw8851b_ctrl_ch(rtwdev, chan, phy_idx);
1470 rtw8851b_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx);
1471 rtw8851b_ctrl_cck_en(rtwdev, cck_en);
1472 rtw8851b_set_nbi_tone_idx(rtwdev, chan);
1473 rtw8851b_set_csi_tone_idx(rtwdev, chan, phy_idx);
1476 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1478 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1480 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0);
1481 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0);
1482 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1484 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0);
1487 chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band);
1488 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx);
1489 rtw8851b_5m_mask(rtwdev, chan, phy_idx);
1490 rtw8851b_set_cfr(rtwdev, chan);
1491 rtw8851b_bb_reset_all(rtwdev, phy_idx);
1494 static void rtw8851b_set_channel(struct rtw89_dev *rtwdev,
1499 rtw8851b_set_channel_mac(rtwdev, chan, mac_idx);
1500 rtw8851b_set_channel_bb(rtwdev, chan, phy_idx);
1501 rtw8851b_set_channel_rf(rtwdev, chan, phy_idx);
1504 static void rtw8851b_tssi_cont_en(struct rtw89_dev *rtwdev, bool en,
1508 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON, 0x0);
1509 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN, 0x0);
1511 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON, 0x1);
1512 rtw89_phy_write32_mask(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN, 0x1);
1516 static void rtw8851b_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en,
1519 rtw8851b_tssi_cont_en(rtwdev, en, RF_PATH_A);
1522 static void rtw8851b_adc_en(struct rtw89_dev *rtwdev, bool en)
1525 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0);
1527 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0xf);
1530 static void rtw8851b_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
1537 rtw89_chip_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL);
1538 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false);
1539 rtw8851b_tssi_cont_en_phyidx(rtwdev, false, RTW89_PHY_0);
1540 rtw8851b_adc_en(rtwdev, false);
1542 rtw8851b_bb_reset_en(rtwdev, chan->band_type, phy_idx, false);
1544 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
1545 rtw8851b_adc_en(rtwdev, true);
1546 rtw8851b_tssi_cont_en_phyidx(rtwdev, true, RTW89_PHY_0);
1547 rtw8851b_bb_reset_en(rtwdev, chan->band_type, phy_idx, true);
1548 rtw89_chip_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en);
1552 static void rtw8851b_rfk_init(struct rtw89_dev *rtwdev)
1554 rtwdev->is_tssi_mode[RF_PATH_A] = false;
1555 rtwdev->is_tssi_mode[RF_PATH_B] = false;
1556 rtw8851b_lck_init(rtwdev);
1558 rtw8851b_dpk_init(rtwdev);
1559 rtw8851b_aack(rtwdev);
1560 rtw8851b_rck(rtwdev);
1561 rtw8851b_dack(rtwdev);
1562 rtw8851b_rx_dck(rtwdev, RTW89_PHY_0);
1565 static void rtw8851b_rfk_channel(struct rtw89_dev *rtwdev)
1569 rtw8851b_rx_dck(rtwdev, phy_idx);
1570 rtw8851b_iqk(rtwdev, phy_idx);
1571 rtw8851b_tssi(rtwdev, phy_idx, true);
1572 rtw8851b_dpk(rtwdev, phy_idx);
1575 static void rtw8851b_rfk_band_changed(struct rtw89_dev *rtwdev,
1578 rtw8851b_tssi_scan(rtwdev, phy_idx);
1581 static void rtw8851b_rfk_scan(struct rtw89_dev *rtwdev, bool start)
1583 rtw8851b_wifi_scan_notify(rtwdev, start, RTW89_PHY_0);
1586 static void rtw8851b_rfk_track(struct rtw89_dev *rtwdev)
1588 rtw8851b_dpk_track(rtwdev);
1589 rtw8851b_lck_track(rtwdev);
1592 static u32 rtw8851b_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,
1611 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1620 static void rtw8851b_set_txpwr_ref(struct rtw89_dev *rtwdev,
1632 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n");
1634 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL,
1637 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n");
1638 val = rtw8851b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm);
1641 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val,
1644 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n");
1645 val = rtw8851b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck);
1648 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val,
1652 static void rtw8851b_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev,
1679 rtw89_warn(rtwdev,
1691 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1693 rtw89_phy_write32_idx(rtwdev, addr, __DFIR_CFG_MASK, param[i],
1703 static void rtw8851b_set_tx_shape(struct rtw89_dev *rtwdev,
1708 u8 regd = rtw89_regd_get(rtwdev, band);
1713 rtw8851b_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_cck, phy_idx);
1715 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG,
1719 static void rtw8851b_set_txpwr(struct rtw89_dev *rtwdev,
1723 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
1724 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
1725 rtw8851b_set_tx_shape(rtwdev, chan, phy_idx);
1726 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
1727 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
1730 static void rtw8851b_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
1733 rtw8851b_set_txpwr_ref(rtwdev, phy_idx);
1737 void rtw8851b_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
1743 rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst);
1747 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_CTRL, mac_idx);
1748 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN);
1750 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx);
1751 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, pw_ofst);
1754 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx);
1755 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, pw_ofst);
1759 rtw8851b_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1763 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333);
1767 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000);
1771 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff);
1775 rtw8851b_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ?
1781 static void rtw8851b_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, bool bt_en)
1783 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
1785 rtw89_phy_write_reg3_tbl(rtwdev, bt_en ? &rtw8851b_btc_preagc_en_defs_tbl :
1790 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1792 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1795 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1797 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1803 static void rtw8851b_ctrl_btg(struct rtw89_dev *rtwdev, bool btg)
1805 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
1808 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1810 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1812 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1814 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1816 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0);
1817 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x1);
1818 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x1);
1819 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1821 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x1);
1823 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1825 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1828 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1830 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1833 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1,
1835 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1,
1838 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xc);
1839 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0);
1840 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0);
1841 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1843 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0);
1847 static void rtw8851b_bb_ctrl_rx_path(struct rtw89_dev *rtwdev,
1850 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
1854 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 1);
1855 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 1);
1856 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 1);
1857 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
1858 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
1859 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4);
1860 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
1861 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
1864 rtw8851b_set_gain_offset(rtwdev, chan->subband_type, RTW89_PHY_0);
1868 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1);
1869 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3);
1873 static void rtw8851b_bb_cfg_txrx_path(struct rtw89_dev *rtwdev)
1875 rtw8851b_bb_ctrl_rx_path(rtwdev, RF_A);
1877 if (rtwdev->hal.rx_nss == 1) {
1878 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
1879 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
1880 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
1881 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
1884 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0);
1887 static u8 rtw8851b_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
1889 if (rtwdev->is_tssi_mode[rf_path]) {
1892 return rtw89_phy_read32_mask(rtwdev, addr, B_TSSI_THER);
1895 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1896 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0);
1897 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
1901 return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
1904 static void rtw8851b_btc_set_rfe(struct rtw89_dev *rtwdev)
1906 struct rtw89_btc *btc = &rtwdev->btc;
1909 module->rfe_type = rtwdev->efuse.rfe_type;
1910 module->cv = rtwdev->hal.cv;
1914 module->kt_ver_adie = rtwdev->hal.acv;
1945 void rtw8851b_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
1950 if (rtwdev->btc.mdinfo.ant.type == BTC_ANT_SHARED) /* 1-Ant */
1953 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group);
1954 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val);
1957 static void rtw8851b_btc_init_cfg(struct rtw89_dev *rtwdev)
1963 const struct rtw89_chip_info *chip = rtwdev->chip;
1964 struct rtw89_btc *btc = &rtwdev->btc;
1970 rtw89_mac_coex_init(rtwdev, &coex_params);
1973 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true);
1974 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true);
1987 rtw89_write_rf(rtwdev, path, RR_WLSEL, RFREG_MASK, 0x0);
1990 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, BIT(17));
1993 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_SS_GROUP, 0x5ff);
1996 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_RX_GROUP, 0x5df);
2002 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x55f);
2004 rtw8851b_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x5ff);
2007 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0);
2011 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM);
2014 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN);
2020 void rtw8851b_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)
2043 rtw89_write32_set(rtwdev, reg, bitmap);
2045 rtw89_write32_clr(rtwdev, reg, bitmap);
2070 rtw8851b_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
2083 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \
2116 s8 rtw8851b_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
2125 void rtw8851b_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
2130 static void rtw8851b_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
2132 struct rtw89_btc *btc = &rtwdev->btc;
2135 rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWE, RFREG_MASK, 0x80000);
2136 rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWA, RFREG_MASK, 0x1);
2137 rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWD1, RFREG_MASK, 0x110);
2141 rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWD0, RFREG_MASK, 0x179c);
2143 rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWD0, RFREG_MASK, 0x208);
2145 rtw89_write_rf(rtwdev, ant->btg_pos, RR_LUTWE, RFREG_MASK, 0x0);
2153 static void rtw8851b_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
2159 struct rtw89_btc *btc = &rtwdev->btc;
2191 rtw89_write_rf(rtwdev, ant->btg_pos, rf->addr, LNA2_51B_MA, val);
2195 static void rtw8851b_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
2206 rtw89_decode_chan_idx(rtwdev, chan, &ch, &band);
2211 static void rtw8851b_query_ppdu(struct rtw89_dev *rtwdev,
2220 for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
2225 rtw8851b_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
2228 static int rtw8851b_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
2232 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN,
2234 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2235 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2236 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2238 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xC7,
2243 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xC7,
2248 rtw89_write8(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_XYN_CYCLE);
2253 static int rtw8851b_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
2259 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN,
2262 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, &wl_rfc_s0);
2266 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, wl_rfc_s0,
2271 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, &wl_rfc_s1);
2275 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, wl_rfc_s1,