Lines Matching refs:gain
481 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
485 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK],
488 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM],
491 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW],
494 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID],
497 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH],
500 gain->offset_valid = valid;
661 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
674 &gain->comp[path][i]);
677 gain->comp_valid = valid;
889 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain;
903 val = gain->lna_gain[gain_band][path][i];
914 val = gain->tia_gain[gain_band][path][i];
975 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain;
979 val = u32_encode_bits(gain->rpl_ofst_20[band][RF_PATH_A], B_P0_RPL1_20_MASK) |
980 u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][0], B_P0_RPL1_40_MASK) |
981 u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][1], B_P0_RPL1_41_MASK);
986 val = u32_encode_bits(gain->rpl_ofst_40[band][RF_PATH_A][2], B_P0_RTL2_42_MASK) |
987 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][0], B_P0_RTL2_80_MASK) |
988 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][1], B_P0_RTL2_81_MASK) |
989 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][10], B_P0_RTL2_8A_MASK);
993 val = u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][2], B_P0_RTL3_82_MASK) |
994 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][3], B_P0_RTL3_83_MASK) |
995 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][4], B_P0_RTL3_84_MASK) |
996 u32_encode_bits(gain->rpl_ofst_80[band][RF_PATH_A][9], B_P0_RTL3_89_MASK);
1442 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1453 gain->offset_base[RTW89_PHY_0] =
1455 gain->rssi_base[RTW89_PHY_0] =