Lines Matching refs:addr
672 u32 addr, u32 mask)
683 addr &= 0xff;
684 direct_addr = base_addr[rf_path] + (addr << 2);
694 enum rtw89_rf_path rf_path, u32 addr, u32 mask)
711 FIELD_PREP(B_SWSI_READ_ADDR_ADDR_V1, addr);
727 u32 addr, u32 mask)
729 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr);
737 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask);
739 return rtw89_phy_read_rf_a(rtwdev, rf_path, addr, mask);
744 u32 addr, u32 mask, u32 data)
755 addr &= 0xff;
756 direct_addr = base_addr[rf_path] + (addr << 2);
769 enum rtw89_rf_path rf_path, u32 addr, u32 mask,
797 FIELD_PREP(B_SWSI_DATA_ADDR_V1, addr) |
806 u32 addr, u32 mask, u32 data)
808 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr);
816 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data);
818 return rtw89_phy_write_rf_a(rtwdev, rf_path, addr, mask, data);
840 if (reg->addr == 0xfe)
842 else if (reg->addr == 0xfd)
844 else if (reg->addr == 0xfc)
846 else if (reg->addr == 0xfb)
848 else if (reg->addr == 0xfa)
850 else if (reg->addr == 0xf9)
853 rtw89_phy_write32(rtwdev, reg->addr, reg->data);
857 u32 addr;
898 arg.addr, data, type);
988 arg.addr, data, bw);
1015 arg.addr, data, type);
1050 arg.addr, data, type);
1061 union rtw89_phy_bb_gain_arg arg = { .addr = reg->addr };
1070 if (arg.addr >= 0xf9 && arg.addr <= 0xfe) {
1096 arg.addr, reg->data, arg.cfg_type);
1117 cpu_to_le32((reg->addr << 20) | reg->data);
1154 u32 addr = reg->addr;
1156 if (addr == 0xfe || addr == 0xfd || addr == 0xfc || addr == 0xfb ||
1157 addr == 0xfa || addr == 0xf9)
1160 if (rtw89_chip_rf_v1(rtwdev) && addr < 0x100)
1172 if (reg->addr == 0xfe) {
1174 } else if (reg->addr == 0xfd) {
1176 } else if (reg->addr == 0xfc) {
1178 } else if (reg->addr == 0xfb) {
1180 } else if (reg->addr == 0xfa) {
1182 } else if (reg->addr == 0xf9) {
1185 rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data);
1196 rtw89_write_rf(rtwdev, rf_path, reg->addr, RFREG_MASK, reg->data);
1198 if (reg->addr < 0x100)
1221 headline = get_phy_headline(reg->addr);
1233 target = get_phy_target(reg->addr);
1244 target = get_phy_target(reg->addr);
1254 rfe_para = get_phy_cond_rfe(reg->addr);
1255 cv_para = get_phy_cond_cv(reg->addr);
1271 rfe_para = get_phy_cond_rfe(reg->addr);
1272 cv_para = get_phy_cond_cv(reg->addr);
1315 cfg_target = get_phy_target(table->regs[headline_idx].addr);
1318 cond = get_phy_cond(reg->addr);
1322 target = get_phy_target(reg->addr);
1328 reg->addr, reg->data);
1446 static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr)
1448 u32 phy_page = addr >> 8;
1452 return addr < 0x10000 ? 0x20000 : 0;
1480 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
1484 addr += rtw89_phy0_phy1_offset(rtwdev, addr);
1485 rtw89_phy_write32_mask(rtwdev, addr, mask, data);
1489 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
1493 addr += rtw89_phy0_phy1_offset(rtwdev, addr);
1494 return rtw89_phy_read32_mask(rtwdev, addr, mask);
1498 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
1501 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0);
1506 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1);
1517 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data);
2109 u32 addr, val;
2121 addr = R_AX_PWR_BY_RATE;
2143 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr,
2145 addr += 4;
2190 u32 addr, val;
2199 addr = R_AX_PWR_LMT;
2205 j += 4, addr += 4, ptr += 4) {
2211 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
2226 u32 addr, val;
2235 addr = R_AX_PWR_RU_LMT;
2241 j += 4, addr += 4, ptr += 4) {
2247 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
2504 rtw89_phy_set_phy_regs(rtwdev, dcfo_comp->addr, dcfo_comp->mask,
3725 u32 addr;
3730 addr = rtw89_phy_get_ie_bitmap_addr(ie_page);
3732 return rtw89_phy_read32(rtwdev, addr);
3740 u32 addr;
3748 addr = rtw89_phy_get_ie_bitmap_addr(ie_page);
3749 rtw89_phy_write32(rtwdev, addr, val);
3856 tmp = rtw89_phy_read32_mask(rtwdev, cfg->table[i].addr,
4077 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_lna_init.addr,
4079 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_lna_init.addr,
4087 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_tia_init.addr,
4089 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_tia_init.addr,
4097 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_rxb_init.addr,
4099 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_rxb_init.addr,
4119 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_p20_pagcugc_en.addr,
4121 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_s20_pagcugc_en.addr,
4123 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_p20_pagcugc_en.addr,
4125 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_s20_pagcugc_en.addr,
4522 rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data);
4528 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data);
4534 rtw89_phy_write32_set(rtwdev, def->addr, def->mask);
4540 rtw89_phy_write32_clr(rtwdev, def->addr, def->mask);
4603 reg = rtw89_mac_reg_by_idx(rtwdev, regs[i].addr, mac_idx);
4665 reg = rtw89_mac_reg_by_idx(rtwdev, regs[i].addr, mac_idx);