Lines Matching defs:ccx
3242 const struct rtw89_ccx_regs *ccx = phy->ccx;
3250 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->en_mask, 1);
3251 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->trig_opt_mask, 1);
3252 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1);
3253 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->edcca_opt_mask,
3370 const struct rtw89_ccx_regs *ccx = phy->ccx;
3373 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_l_mask,
3375 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_l_mask,
3377 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_l_mask,
3379 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_l_mask,
3382 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_h_mask,
3384 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_h_mask,
3386 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_h_mask,
3388 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_h_mask,
3401 const struct rtw89_ccx_regs *ccx = phy->ccx;
3411 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_collect_en_mask, true);
3412 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_en_mask, true);
3413 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_en_mask, true);
3414 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_en_mask, true);
3415 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_en_mask, true);
3444 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n",
3454 const struct rtw89_ccx_regs *ccx = phy->ccx;
3456 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 0);
3457 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 0);
3458 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 1);
3459 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1);
3533 const struct rtw89_ccx_regs *ccx = phy->ccx;
3536 if (rtw89_phy_read32_mask(rtwdev, ccx->ifs_total_addr,
3537 ccx->ifs_cnt_done_mask) == 0) {
3544 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_tx_cnt_addr,
3545 ccx->ifs_clm_tx_cnt_msk);
3547 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_tx_cnt_addr,
3548 ccx->ifs_clm_edcca_excl_cca_fa_mask);
3550 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_cca_addr,
3551 ccx->ifs_clm_cckcca_excl_fa_mask);
3553 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_cca_addr,
3554 ccx->ifs_clm_ofdmcca_excl_fa_mask);
3556 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_fa_addr,
3557 ccx->ifs_clm_cck_fa_mask);
3559 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_fa_addr,
3560 ccx->ifs_clm_ofdm_fa_mask);
3563 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr,
3564 ccx->ifs_t1_his_mask);
3566 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr,
3567 ccx->ifs_t2_his_mask);
3569 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr,
3570 ccx->ifs_t3_his_mask);
3572 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr,
3573 ccx->ifs_t4_his_mask);
3576 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_l_addr,
3577 ccx->ifs_t1_avg_mask);
3579 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_l_addr,
3580 ccx->ifs_t2_avg_mask);
3582 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_h_addr,
3583 ccx->ifs_t3_avg_mask);
3585 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_h_addr,
3586 ccx->ifs_t4_avg_mask);
3589 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_l_addr,
3590 ccx->ifs_t1_cca_mask);
3592 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_l_addr,
3593 ccx->ifs_t2_cca_mask);
3595 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_h_addr,
3596 ccx->ifs_t3_cca_mask);
3598 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_h_addr,
3599 ccx->ifs_t4_cca_mask);
3602 rtw89_phy_read32_mask(rtwdev, ccx->ifs_total_addr,
3603 ccx->ifs_total_mask);
3633 const struct rtw89_ccx_regs *ccx = phy->ccx;
3649 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr,
3650 ccx->ifs_clm_period_mask, period);
3651 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr,
3652 ccx->ifs_clm_cnt_unit_mask,
4834 .ccx = &rtw89_ccx_regs_ax,