Lines Matching refs:ret
25 int ret;
30 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_RST_BDRAM),
34 if (ret)
241 int ret;
246 ret = rtw89_pci_rxbd_info_update(rtwdev, skb);
247 if (ret) {
249 bd_ring->wp, ret);
529 int ret;
534 ret = rtw89_pci_rxbd_info_update(rtwdev, skb);
535 if (ret) {
537 bd_ring->wp, ret);
1211 int ret;
1216 ret = -EBUSY;
1248 return ret;
1293 int ret;
1305 ret = -ENOSPC;
1309 ret = rtw89_pci_txwd_submit(rtwdev, tx_ring, txwd, tx_req);
1310 if (ret) {
1328 return ret;
1338 int ret = 0;
1355 ret = -ENOSPC;
1360 ret = rtw89_pci_txbd_submit(rtwdev, tx_ring, txbd, tx_req);
1361 if (ret) {
1371 return ret;
1377 int ret;
1379 ret = rtw89_pci_tx_write(rtwdev, tx_req, desc_info->ch_dma);
1380 if (ret) {
1382 return ret;
1745 int ret;
1747 ret = rtw89_pci_check_mdio(rtwdev, addr, speed, B_AX_MDIO_RFLAG);
1748 if (ret) {
1749 rtw89_err(rtwdev, "[ERR]MDIO R16 0x%X fail ret=%d!\n", addr, ret);
1750 return ret;
1760 int ret;
1763 ret = rtw89_pci_check_mdio(rtwdev, addr, speed, B_AX_MDIO_WFLAG);
1764 if (ret) {
1765 rtw89_err(rtwdev, "[ERR]MDIO W16 0x%X = %x fail ret=%d!\n", addr, data, ret);
1766 return ret;
1776 int ret;
1779 ret = rtw89_read16_mdio(rtwdev, addr, speed, &val);
1780 if (ret)
1781 return ret;
1787 ret = rtw89_write16_mdio(rtwdev, addr, val, speed);
1788 if (ret)
1789 return ret;
1796 int ret;
1799 ret = rtw89_read16_mdio(rtwdev, addr, speed, &val);
1800 if (ret)
1801 return ret;
1802 ret = rtw89_write16_mdio(rtwdev, addr, val | mask, speed);
1803 if (ret)
1804 return ret;
1811 int ret;
1814 ret = rtw89_read16_mdio(rtwdev, addr, speed, &val);
1815 if (ret)
1816 return ret;
1817 ret = rtw89_write16_mdio(rtwdev, addr, val & ~mask, speed);
1818 if (ret)
1819 return ret;
1846 int ret;
1848 ret = rtw89_pci_read_config_byte(rtwdev, addr, &value);
1849 if (ret)
1850 return ret;
1853 ret = rtw89_pci_write_config_byte(rtwdev, addr, value);
1855 return ret;
1862 int ret;
1864 ret = rtw89_pci_read_config_byte(rtwdev, addr, &value);
1865 if (ret)
1866 return ret;
1869 ret = rtw89_pci_write_config_byte(rtwdev, addr, value);
1871 return ret;
1878 int ret;
1881 ret = rtw89_read16_mdio(rtwdev, RAC_CTRL_PPR_V1, phy_rate, &val);
1882 if (ret)
1883 return ret;
1884 ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, val & ~B_AX_CLK_CALIB_EN,
1886 if (ret)
1887 return ret;
1888 ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, val | B_AX_CLK_CALIB_EN,
1890 if (ret)
1891 return ret;
1895 ret = rtw89_read16_mdio(rtwdev, RAC_CTRL_PPR_V1, phy_rate, &tar);
1896 if (ret)
1897 return ret;
1898 ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, val & ~B_AX_CLK_CALIB_EN,
1900 if (ret)
1901 return ret;
1917 int ret;
1922 ret = rtw89_write16_mdio_mask(rtwdev, RAC_REG_FLD_0, BAC_AUTOK_N_MASK,
1924 return ret;
1934 int ret = 0;
1939 ret = rtw89_pci_read_config_byte(rtwdev, RTW89_PCIE_PHY_RATE, &val8);
1940 if (ret) {
1943 return ret;
1955 ret = rtw89_pci_read_config_byte(rtwdev, RTW89_PCIE_L1_CTRL, &bdr_ori);
1956 if (ret) {
1958 return ret;
1962 ret = rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_L1_CTRL,
1964 if (ret) {
1967 return ret;
1972 ret = rtw89_read16_mdio(rtwdev, RAC_CTRL_PPR_V1, phy_rate, &val16);
1973 if (ret) {
1979 ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1,
1981 if (ret) {
1990 ret = rtw89_write16_mdio_clr(rtwdev, RAC_CTRL_PPR_V1, B_AX_DIV, phy_rate);
1991 if (ret) {
1997 ret = __get_target(rtwdev, &tar, phy_rate);
1998 if (ret) {
1999 rtw89_err(rtwdev, "[ERR]1st get target fail %d\n", ret);
2024 ret = rtw89_read16_mdio(rtwdev, RAC_CTRL_PPR_V1, phy_rate, &val16);
2025 if (ret) {
2032 ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, val16, phy_rate);
2033 if (ret) {
2038 ret = __get_target(rtwdev, &tar, phy_rate);
2039 if (ret) {
2040 rtw89_err(rtwdev, "[ERR]2nd get target fail %d\n", ret);
2046 ret = rtw89_write16_mdio(rtwdev, RAC_SET_PPR_V1,
2048 if (ret) {
2054 ret = rtw89_write16_mdio_set(rtwdev, RAC_CTRL_PPR_V1, B_AX_CALIB_EN, phy_rate);
2055 if (ret) {
2061 ret = rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_CLK_CTRL,
2067 ret = rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_L1_CTRL,
2069 if (ret) {
2072 return ret;
2076 return ret;
2082 int ret;
2085 ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA24, B_AX_DEGLITCH,
2087 if (ret)
2088 return ret;
2089 ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA24, B_AX_DEGLITCH,
2091 if (ret)
2092 return ret;
2123 int ret;
2128 ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA26, B_AX_RXEN,
2130 if (ret)
2131 return ret;
2133 ret = rtw89_write16_mdio_clr(rtwdev, RAC_ANA26, B_AX_RXEN,
2135 if (ret)
2136 return ret;
2332 u32 ret, check, dma_busy;
2338 ret = read_poll_timeout(rtw89_read32, dma_busy, (dma_busy & check) == 0,
2340 if (ret)
2341 return ret;
2348 ret = read_poll_timeout(rtw89_read32, dma_busy, (dma_busy & check) == 0,
2350 if (ret)
2351 return ret;
2359 u32 ret, check, dma_busy;
2364 ret = read_poll_timeout(rtw89_read32, dma_busy, (dma_busy & check) == 0,
2366 if (ret)
2367 return ret;
2374 u32 ret;
2376 ret = rtw89_poll_txdma_ch_idle_pcie(rtwdev);
2377 if (ret) {
2379 return ret;
2382 ret = rtw89_poll_rxdma_ch_idle_pcie(rtwdev);
2383 if (ret) {
2385 return ret;
2498 int ret;
2503 ret = rtw89_pci_l2_rxen_lat(rtwdev);
2504 if (ret) {
2505 rtw89_err(rtwdev, "[ERR] pcie l2 rxen lat %d\n", ret);
2506 return ret;
2513 ret = rtw89_pci_autok_x(rtwdev);
2514 if (ret) {
2515 rtw89_err(rtwdev, "[ERR] pcie autok_x fail %d\n", ret);
2516 return ret;
2519 ret = rtw89_pci_auto_refclk_cal(rtwdev, false);
2520 if (ret) {
2521 rtw89_err(rtwdev, "[ERR] pcie autok fail %d\n", ret);
2522 return ret;
2542 ret = rtw89_pci_poll_dma_all_idle(rtwdev);
2543 if (ret) {
2545 return ret;
2554 ret = rtw89_pci_rst_bdram_pcie(rtwdev);
2555 if (ret) {
2557 return ret;
2656 int ret;
2658 ret = info->ltr_set(rtwdev, true);
2659 if (ret) {
2661 return ret;
2688 int ret;
2690 ret = pci_enable_device(pdev);
2691 if (ret) {
2693 return ret;
2716 int ret;
2718 ret = pci_request_regions(pdev, KBUILD_MODNAME);
2719 if (ret) {
2724 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
2725 if (ret) {
2730 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
2731 if (ret) {
2740 ret = -EIO;
2749 return ret;
2950 int ret;
2952 ret = rtw89_pci_alloc_tx_wd_ring(rtwdev, pdev, tx_ring, txch);
2953 if (ret) {
2958 ret = rtw89_pci_get_txch_addrs(rtwdev, txch, &txch_addr);
2959 if (ret) {
2966 ret = -ENOMEM;
2985 return ret;
2997 int ret;
3005 ret = rtw89_pci_alloc_tx_ring(rtwdev, pdev, tx_ring,
3007 if (ret) {
3022 return ret;
3037 int ret;
3039 ret = rtw89_pci_get_rxch_addrs(rtwdev, rxch, &rxch_addr);
3040 if (ret) {
3042 return ret;
3047 ret = -ENOMEM;
3065 ret = -ENOMEM;
3071 ret = rtw89_pci_init_rx_bd(rtwdev, pdev, rx_ring, skb,
3073 if (ret) {
3101 return ret;
3112 int ret;
3118 ret = rtw89_pci_alloc_rx_ring(rtwdev, pdev, rx_ring,
3120 if (ret) {
3135 return ret;
3141 int ret;
3143 ret = rtw89_pci_alloc_tx_rings(rtwdev, pdev);
3144 if (ret) {
3149 ret = rtw89_pci_alloc_rx_rings(rtwdev, pdev);
3150 if (ret) {
3160 return ret;
3174 int ret;
3176 ret = rtw89_pci_setup_mapping(rtwdev, pdev);
3177 if (ret) {
3182 ret = rtw89_pci_alloc_trx_rings(rtwdev, pdev);
3183 if (ret) {
3198 return ret;
3297 int ret;
3300 ret = pci_alloc_irq_vectors(pdev, 1, 1, flags);
3301 if (ret < 0) {
3302 rtw89_err(rtwdev, "failed to alloc irq vectors, ret %d\n", ret);
3306 ret = devm_request_threaded_irq(rtwdev->dev, pdev->irq,
3310 if (ret) {
3322 return ret;
3353 int ret;
3362 ret = pci_read_config_dword(pdev, RTW89_PCIE_L1_STS_V1, &val);
3363 if (ret)
3364 return ret;
3405 int ret;
3410 ret = rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_CLK_CTRL,
3412 if (ret)
3417 ret = rtw89_pci_config_byte_set(rtwdev,
3421 ret = rtw89_pci_config_byte_clr(rtwdev,
3424 if (ret)
3425 rtw89_err(rtwdev, "failed to %s CLKREQ_L1, ret=%d",
3426 enable ? "set" : "unset", ret);
3443 int ret;
3448 ret = rtw89_pci_read_config_byte(rtwdev, RTW89_PCIE_ASPM_CTRL, &value);
3449 if (ret)
3456 ret = rtw89_pci_write_config_byte(rtwdev, RTW89_PCIE_ASPM_CTRL, value);
3457 if (ret)
3462 ret = rtw89_pci_config_byte_set(rtwdev,
3466 ret = rtw89_pci_config_byte_clr(rtwdev,
3477 if (ret)
3478 rtw89_err(rtwdev, "failed to %s ASPM L1, ret=%d",
3479 enable ? "set" : "unset", ret);
3504 int ret;
3522 ret = pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &link_ctrl);
3523 if (ret) {
3524 rtw89_err(rtwdev, "failed to read PCI cap, ret=%d\n", ret);
3538 int ret;
3542 ret = rtw89_pci_config_byte_set(rtwdev,
3546 ret = rtw89_pci_config_byte_clr(rtwdev,
3549 if (ret)
3550 rtw89_err(rtwdev, "failed to %s L1SS, ret=%d",
3551 enable ? "set" : "unset", ret);
3553 ret = rtw89_pci_config_byte_clr(rtwdev, RTW89_PCIE_L1SS_STS_V1,
3556 if (ret)
3557 rtw89_warn(rtwdev, "failed to unset ASPM L1.1, ret=%d", ret);
3588 int ret = 0;
3592 ret = read_poll_timeout_atomic(rtw89_read32, sts, (sts & busy) == 0x0,
3595 if (ret) {
3600 return ret;
3606 int ret;
3612 ret = rtw89_pci_poll_io_idle(rtwdev);
3613 if (ret) {
3623 ret = rtw89_pci_poll_io_idle(rtwdev);
3630 return ret;
3637 int ret = 0;
3643 ret = read_poll_timeout_atomic(rtw89_read32, sts,
3646 return ret;
3651 u32 ret;
3660 ret = rtw89_pci_rst_bdram(rtwdev);
3661 if (ret)
3662 return ret;
3665 return ret;
3671 int ret;
3675 ret = rtw89_pci_lv1rst_stop_dma(rtwdev);
3676 if (ret)
3682 ret = rtw89_pci_lv1rst_start_dma(rtwdev);
3683 if (ret)
3691 return ret;
3841 int ret;
3863 ret = rtw89_core_init(rtwdev);
3864 if (ret) {
3869 ret = rtw89_pci_claim_device(rtwdev, pdev);
3870 if (ret) {
3875 ret = rtw89_pci_setup_resource(rtwdev, pdev);
3876 if (ret) {
3881 ret = rtw89_chip_info_setup(rtwdev);
3882 if (ret) {
3893 ret = rtw89_pci_request_irq(rtwdev, pdev);
3894 if (ret) {
3899 ret = rtw89_core_register(rtwdev);
3900 if (ret) {
3920 return ret;