Lines Matching defs:val
24 u32 val;
30 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_RST_BDRAM),
1598 u32 val = readl(rtwpci->mmap + addr);
1602 if (val != RTW89_R32_DEAD)
1603 return val;
1605 rtw89_warn(rtwdev, "addr %#x = %#x\n", addr, val);
1609 val = readl(rtwpci->mmap + addr);
1612 return val;
1713 u16 val;
1717 val = rtw89_read16(rtwdev, R_AX_MDIO_CFG);
1721 val = u16_replace_bits(val, MDIO_PG0_G1, B_AX_MDIO_PHY_ADDR_MASK);
1723 val = u16_replace_bits(val, MDIO_PG1_G1, B_AX_MDIO_PHY_ADDR_MASK);
1727 val = u16_replace_bits(val, MDIO_PG0_G2, B_AX_MDIO_PHY_ADDR_MASK);
1729 val = u16_replace_bits(val, MDIO_PG1_G2, B_AX_MDIO_PHY_ADDR_MASK);
1735 rtw89_write16(rtwdev, R_AX_MDIO_CFG, val);
1738 return read_poll_timeout(rtw89_read16, val, !(val & rw_bit), 10, 2000,
1743 rtw89_read16_mdio(struct rtw89_dev *rtwdev, u8 addr, u8 speed, u16 *val)
1752 *val = rtw89_read16(rtwdev, R_AX_MDIO_RDATA);
1777 u16 val;
1779 ret = rtw89_read16_mdio(rtwdev, addr, speed, &val);
1784 val &= ~mask;
1785 val |= ((data << shift) & mask);
1787 ret = rtw89_write16_mdio(rtwdev, addr, val, speed);
1797 u16 val;
1799 ret = rtw89_read16_mdio(rtwdev, addr, speed, &val);
1802 ret = rtw89_write16_mdio(rtwdev, addr, val | mask, speed);
1812 u16 val;
1814 ret = rtw89_read16_mdio(rtwdev, addr, speed, &val);
1817 ret = rtw89_write16_mdio(rtwdev, addr, val & ~mask, speed);
1877 u16 val, tar;
1881 ret = rtw89_read16_mdio(rtwdev, RAC_CTRL_PPR_V1, phy_rate, &val);
1884 ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, val & ~B_AX_CLK_CALIB_EN,
1888 ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, val | B_AX_CLK_CALIB_EN,
1898 ret = rtw89_write16_mdio(rtwdev, RAC_CTRL_PPR_V1, val & ~B_AX_CLK_CALIB_EN,
2311 u32 val = B_AX_CLR_ACH0_IDX | B_AX_CLR_ACH1_IDX | B_AX_CLR_ACH2_IDX |
2318 val |= B_AX_CLR_ACH4_IDX | B_AX_CLR_ACH5_IDX |
2321 rtw89_write32_set(rtwdev, R_AX_TXBD_RWPTR_CLR1, val);
2572 u32 val;
2577 val = rtw89_read32(rtwdev, R_AX_LTR_CTRL_0);
2578 if (rtw89_pci_ltr_is_err_reg_val(val))
2580 val = rtw89_read32(rtwdev, R_AX_LTR_CTRL_1);
2581 if (rtw89_pci_ltr_is_err_reg_val(val))
2583 val = rtw89_read32(rtwdev, R_AX_LTR_IDLE_LATENCY);
2584 if (rtw89_pci_ltr_is_err_reg_val(val))
2586 val = rtw89_read32(rtwdev, R_AX_LTR_ACTIVE_LATENCY);
2587 if (rtw89_pci_ltr_is_err_reg_val(val))
3352 u32 val, phy_offset;
3358 val = rtw89_read32_mask(rtwdev, R_AX_PCIE_MIX_CFG_V1, B_AX_ASPM_CTRL_MASK);
3359 if (val == B_AX_ASPM_CTRL_L1)
3362 ret = pci_read_config_dword(pdev, RTW89_PCIE_L1_STS_V1, &val);
3366 val = FIELD_GET(RTW89_BCFG_LINK_SPEED_MASK, val);
3367 if (val == RTW89_PCIE_GEN1_SPEED) {
3369 } else if (val == RTW89_PCIE_GEN2_SPEED) {
3487 u32 val = 0;
3491 val = B_AX_RXMIT_RXP2_SEL | B_AX_RXMIT_RXP1_SEL |
3496 rtw89_write32(rtwdev, R_AX_INT_MIT_RX, val);
3605 u32 val;
3614 val = rtw89_read32(rtwdev, R_AX_DBG_ERR_FLAG);
3617 R_AX_DBG_ERR_FLAG, val);
3618 if (val & B_AX_TX_STUCK || val & B_AX_PCIE_TXBD_LEN0)
3620 if (val & B_AX_RX_STUCK)
3624 val = rtw89_read32(rtwdev, R_AX_DBG_ERR_FLAG);
3627 R_AX_DBG_ERR_FLAG, val);