Lines Matching refs:rtwdev
39 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset,
42 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
45 rtw89_write32(rtwdev, mac->filter_model_addr, addr);
46 rtw89_write32(rtwdev, mac->indir_access_addr, val);
49 static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset,
52 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
55 rtw89_write32(rtwdev, mac->filter_model_addr, addr);
56 return rtw89_read32(rtwdev, mac->indir_access_addr);
59 int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 mac_idx,
65 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN);
68 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN);
71 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND);
83 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val)
89 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3);
91 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n");
93 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val);
94 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset);
99 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val)
105 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3);
107 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n");
109 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset);
110 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA);
116 int dle_dfi_ctrl(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl)
138 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type);
142 rtw89_write32(rtwdev, ctrl_reg, ctrl_data);
145 1, 1000, false, rtwdev, ctrl_reg);
147 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n",
152 ctrl->out_data = rtw89_read32(rtwdev, data_reg);
156 static int dle_dfi_quota(struct rtw89_dev *rtwdev,
165 ret = dle_dfi_ctrl(rtwdev, &ctrl);
167 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret);
176 static int dle_dfi_qempty(struct rtw89_dev *rtwdev,
185 ret = dle_dfi_ctrl(rtwdev, &ctrl);
187 rtw89_warn(rtwdev, "[ERR]dle_dfi_ctrl %d\n", ret);
195 static void dump_err_status_dispatcher(struct rtw89_dev *rtwdev)
197 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ",
198 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR));
199 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n",
200 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR));
201 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ",
202 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR));
203 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n",
204 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR));
205 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ",
206 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR));
207 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n",
208 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR));
211 static void rtw89_mac_dump_qta_lost(struct rtw89_dev *rtwdev)
222 ret = dle_dfi_qempty(rtwdev, &qempty);
224 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
226 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty);
235 ret = dle_dfi_ctrl(rtwdev, &ctrl);
237 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
239 rtw89_info(rtwdev, "qidx%d pktcnt = %ld\n", i,
246 ret = dle_dfi_quota(rtwdev, "a);
248 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__);
250 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n",
253 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG);
254 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%lx\n",
256 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%lx\n",
259 dump_err_status_dispatcher(rtwdev);
262 static void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev,
267 dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO);
272 rtw89_info(rtwdev, "quota lost!\n");
273 rtw89_mac_dump_qta_lost(rtwdev);
280 static void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev)
282 const struct rtw89_chip_info *chip = rtwdev->chip;
286 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL);
288 rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n");
292 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR);
293 rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err);
294 rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n",
295 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR));
298 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n",
299 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1));
300 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n",
301 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1));
303 rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n",
304 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG));
305 rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n",
306 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG));
307 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n",
308 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN));
309 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n",
310 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS));
315 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n",
316 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR));
317 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n",
318 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR));
320 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n",
321 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1));
323 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n",
324 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX));
329 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n",
330 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR));
331 rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n",
332 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG));
333 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n",
334 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL));
335 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n",
336 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC));
337 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n",
338 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS));
339 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n",
340 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA));
341 rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n",
342 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1));
343 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n",
344 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG));
345 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n",
346 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG));
348 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL,
350 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL,
352 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1,
355 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL,
357 rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n",
358 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2));
361 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n",
362 rtw89_read32(rtwdev, R_AX_SEC_DEBUG));
363 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n",
364 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL));
365 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n",
366 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC));
367 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n",
368 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS));
369 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n",
370 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA));
371 rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n",
372 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA));
373 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n",
374 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG));
375 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n",
376 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG));
377 rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n",
378 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT));
379 rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n",
380 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT));
385 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n",
386 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR));
387 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n",
388 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR));
389 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n",
390 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR));
391 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n",
392 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR));
396 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n",
397 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR));
398 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n",
399 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR));
403 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n",
404 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR));
405 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n",
406 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
407 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n",
408 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR));
409 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
410 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
415 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n",
416 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR));
417 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n",
418 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR));
419 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n",
420 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR));
421 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n",
422 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR));
424 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n",
425 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR));
426 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n",
427 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1));
432 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n",
433 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR));
434 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n",
435 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
436 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n",
437 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR));
438 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
439 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
440 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n",
441 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0));
442 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n",
443 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1));
444 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n",
445 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2));
446 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n",
447 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS));
448 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n",
449 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0));
450 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n",
451 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1));
452 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n",
453 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2));
454 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n",
455 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS));
457 rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n",
458 rtw89_read32(rtwdev, R_AX_RX_CTRL0));
459 rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n",
460 rtw89_read32(rtwdev, R_AX_RX_CTRL1));
461 rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n",
462 rtw89_read32(rtwdev, R_AX_RX_CTRL2));
464 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n",
465 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0));
466 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n",
467 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1));
468 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n",
469 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2));
474 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n",
475 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR));
476 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n",
477 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR));
481 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n",
482 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR));
483 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n",
484 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR));
485 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n",
486 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR));
487 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n",
488 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR));
489 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n",
490 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR));
491 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n",
492 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR));
497 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n",
498 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR));
499 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n",
500 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR));
501 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n",
502 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR));
503 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n",
504 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR));
505 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n",
506 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR));
507 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n",
508 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR));
510 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n",
511 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR));
512 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n",
513 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR));
514 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n",
515 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR));
516 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n",
517 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR));
518 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n",
519 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR));
524 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n",
525 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK));
526 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n",
527 rtw89_read32(rtwdev, R_AX_HAXI_IDCT));
531 static void rtw89_mac_dump_cmac_err_status(struct rtw89_dev *rtwdev,
534 const struct rtw89_chip_info *chip = rtwdev->chip;
539 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL);
542 rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n");
544 rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n");
551 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset);
552 rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band,
553 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset));
554 rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band,
555 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset));
556 rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band,
557 rtw89_read32(rtwdev, R_AX_CK_EN + offset));
560 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band,
561 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset));
562 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band,
563 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset));
567 rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band,
568 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset));
569 rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band,
570 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset));
575 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band,
576 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset));
577 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band,
578 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset));
580 rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band,
581 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset));
587 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band,
588 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset));
589 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band,
590 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset));
592 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band,
593 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset));
598 rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band,
599 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset));
600 rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band,
601 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset));
606 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band,
607 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset));
608 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band,
609 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset));
611 rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band,
612 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset));
614 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band,
615 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset));
618 rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band,
619 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset));
622 static void rtw89_mac_dump_err_status(struct rtw89_dev *rtwdev,
632 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err);
633 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n",
634 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO));
636 rtw89_mac_dump_dmac_err_status(rtwdev);
637 rtw89_mac_dump_cmac_err_status(rtwdev, RTW89_MAC_0);
638 if (rtwdev->dbcc_en)
639 rtw89_mac_dump_cmac_err_status(rtwdev, RTW89_MAC_1);
641 rtwdev->hci.ops->dump_err_status(rtwdev);
644 rtw89_mac_dump_l0_to_l1(rtwdev, err);
646 rtw89_info(rtwdev, "<---\n");
649 static bool rtw89_mac_suppress_log(struct rtw89_dev *rtwdev, u32 err)
651 struct rtw89_ser *ser = &rtwdev->ser;
655 if (rtwdev->chip->chip_id == RTL8852C) {
656 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL);
661 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR);
662 imr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR);
663 isr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR);
682 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev)
688 false, rtwdev, R_AX_HALT_C2H_CTRL);
690 rtw89_warn(rtwdev, "Polling FW err status fail\n");
694 err = rtw89_read32(rtwdev, R_AX_HALT_C2H);
695 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0);
705 if (rtw89_mac_suppress_log(rtwdev, err))
708 rtw89_fw_st_dbg_dump(rtwdev);
709 rtw89_mac_dump_err_status(rtwdev, err);
715 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err)
717 struct rtw89_ser *ser = &rtwdev->ser;
722 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err);
727 100000, false, rtwdev, R_AX_HALT_H2C_CTRL);
729 rtw89_err(rtwdev, "FW doesn't receive previous msg\n");
733 rtw89_write32(rtwdev, R_AX_HALT_H2C, err);
739 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER);
745 static int hfc_reset_param(struct rtw89_dev *rtwdev)
747 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
749 u8 qta_mode = rtwdev->mac.dle_info.qta_mode;
751 switch (rtwdev->hci.type) {
753 param_ini = rtwdev->chip->hfc_param_ini[qta_mode];
776 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch)
778 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
795 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev)
797 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
802 if (rtwdev->chip->chip_id == RTL8852A)
811 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev)
813 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
822 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch)
824 const struct rtw89_chip_info *chip = rtwdev->chip;
826 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
831 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
835 ret = hfc_ch_cfg_chk(rtwdev, ch);
845 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val);
850 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch)
852 const struct rtw89_chip_info *chip = rtwdev->chip;
854 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
860 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
867 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4);
877 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev)
879 const struct rtw89_chip_info *chip = rtwdev->chip;
881 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg;
885 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
889 ret = hfc_pub_cfg_chk(rtwdev);
895 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val);
898 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val);
903 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev)
905 const struct rtw89_chip_info *chip = rtwdev->chip;
907 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
914 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
918 val = rtw89_read32(rtwdev, regs->pub_page_info1);
921 val = rtw89_read32(rtwdev, regs->pub_page_info3);
925 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2),
928 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1),
931 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl);
944 val = rtw89_read32(rtwdev, regs->ch_page_ctrl);
948 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2);
951 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1);
955 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2);
958 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1);
962 ret = hfc_pub_info_chk(rtwdev);
969 static void hfc_h2c_cfg(struct rtw89_dev *rtwdev)
971 const struct rtw89_chip_info *chip = rtwdev->chip;
973 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
978 rtw89_write32(rtwdev, regs->ch_page_ctrl, val);
980 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl,
985 static void hfc_mix_cfg(struct rtw89_dev *rtwdev)
987 const struct rtw89_chip_info *chip = rtwdev->chip;
989 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
996 rtw89_write32(rtwdev, regs->ch_page_ctrl, val);
999 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val);
1005 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val);
1007 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl),
1017 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val);
1020 static void hfc_func_en(struct rtw89_dev *rtwdev, bool en, bool h2c_en)
1022 const struct rtw89_chip_info *chip = rtwdev->chip;
1024 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param;
1027 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl);
1033 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val);
1036 static int hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en)
1038 const struct rtw89_chip_info *chip = rtwdev->chip;
1044 ret = hfc_reset_param(rtwdev);
1048 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
1052 hfc_func_en(rtwdev, false, false);
1055 hfc_h2c_cfg(rtwdev);
1056 hfc_func_en(rtwdev, en, h2c_en);
1063 ret = hfc_ch_ctrl(rtwdev, ch);
1068 ret = hfc_pub_ctrl(rtwdev);
1072 hfc_mix_cfg(rtwdev);
1074 hfc_func_en(rtwdev, en, h2c_en);
1080 ret = hfc_upd_ch_info(rtwdev, ch);
1084 ret = hfc_upd_mix_info(rtwdev);
1090 static int pwr_cmd_poll(struct rtw89_dev *rtwdev,
1099 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr);
1104 rtw89_warn(rtwdev, "[ERR] Polling timeout\n");
1105 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr);
1106 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val);
1111 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk,
1130 val = rtw89_read8(rtwdev, addr);
1134 rtw89_write8(rtwdev, addr, val);
1137 if (pwr_cmd_poll(rtwdev, cur_cfg))
1154 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev,
1160 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv),
1170 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev)
1174 switch (rtwdev->ps_mode) {
1191 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev,
1197 spin_lock_bh(&rtwdev->rpwm_lock);
1199 request = rtw89_read16(rtwdev, R_AX_RPWM);
1206 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) &
1209 rtwdev->mac.rpwm_seq_num);
1214 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request);
1216 spin_unlock_bh(&rtwdev->rpwm_lock);
1219 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev,
1234 if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K))
1245 rpwm_req_num = rtwdev->mac.rpwm_seq_num;
1246 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr,
1252 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) &
1255 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM);
1256 if (cpwm_seq != rtwdev->mac.cpwm_seq_num)
1259 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE);
1266 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter)
1274 state = rtw89_mac_get_req_pwr_state(rtwdev);
1279 rtw89_mac_send_rpwm(rtwdev, state, false);
1282 rtwdev, state);
1287 rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n",
1290 rtw89_debug(rtwdev, RTW89_DBG_UNEXP,
1296 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev)
1300 state = rtw89_mac_get_req_pwr_state(rtwdev);
1301 rtw89_mac_send_rpwm(rtwdev, state, true);
1304 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on)
1307 const struct rtw89_chip_info *chip = rtwdev->chip;
1309 int (*cfg_func)(struct rtw89_dev *rtwdev);
1321 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags))
1322 __rtw89_leave_ps_mode(rtwdev);
1324 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK);
1326 rtw89_err(rtwdev, "MAC has already powered on\n");
1330 ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq);
1335 set_bit(RTW89_FLAG_POWERON, rtwdev->flags);
1336 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR);
1338 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags);
1339 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags);
1340 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR);
1341 rtw89_set_entity_state(rtwdev, false);
1348 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev)
1350 rtw89_mac_power_switch(rtwdev, false);
1353 static int cmac_func_en(struct rtw89_dev *rtwdev, u8 mac_idx, bool en)
1376 rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en);
1377 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
1379 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
1382 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en);
1383 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en);
1385 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en);
1386 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en);
1388 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
1390 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
1392 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en);
1399 static int dmac_func_en(struct rtw89_dev *rtwdev)
1401 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
1420 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32);
1426 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32);
1431 static int chip_func_en(struct rtw89_dev *rtwdev)
1433 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
1436 rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0,
1442 static int rtw89_mac_sys_init(struct rtw89_dev *rtwdev)
1446 ret = dmac_func_en(rtwdev);
1450 ret = cmac_func_en(rtwdev, 0, true);
1454 ret = chip_func_en(rtwdev);
1528 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev,
1531 struct rtw89_mac_info *mac = &rtwdev->mac;
1534 cfg = &rtwdev->chip->dle_mem[mode];
1539 rtw89_warn(rtwdev, "qta mode unmatch!\n");
1551 static bool mac_is_txq_empty(struct rtw89_dev *rtwdev)
1557 qnum = rtwdev->chip->wde_qempty_acq_num;
1562 ret = dle_dfi_qempty(rtwdev, &qempty);
1564 rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret);
1576 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_sel;
1577 ret = dle_dfi_qempty(rtwdev, &qempty);
1579 rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret);
1586 if (rtwdev->dbcc_en) {
1600 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0);
1612 static u32 dle_expected_used_size(struct rtw89_dev *rtwdev,
1615 u32 size = rtwdev->chip->fifo_size;
1618 size -= rtwdev->chip->dle_scc_rsvd_size;
1623 static void dle_func_en(struct rtw89_dev *rtwdev, bool enable)
1626 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,
1629 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN,
1633 static void dle_clk_en(struct rtw89_dev *rtwdev, bool enable)
1638 if (rtwdev->chip->chip_id == RTL8851B)
1640 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, val);
1642 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, val);
1646 static int dle_mix_cfg(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg)
1652 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG);
1666 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n");
1673 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val);
1675 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG);
1683 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n");
1698 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val);
1708 rtw89_write32(rtwdev, \
1715 static void wde_quota_cfg(struct rtw89_dev *rtwdev,
1730 static void ple_quota_cfg(struct rtw89_dev *rtwdev,
1747 if (rtwdev->chip->chip_id == RTL8852C)
1751 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow)
1757 if (rtwdev->chip->chip_id == RTL8852C)
1760 if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) {
1761 rtw89_err(rtwdev, "[ERR]support SCC mode only\n");
1766 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW);
1768 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC);
1770 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n");
1783 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable)
1788 rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32);
1790 rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32);
1793 static void dle_quota_cfg(struct rtw89_dev *rtwdev,
1797 wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu);
1798 ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt);
1801 static int dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode,
1809 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
1813 cfg = get_dle_mem_cfg(rtwdev, mode);
1815 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n");
1821 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode);
1823 rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n",
1832 dle_expected_used_size(rtwdev, mode)) {
1833 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n");
1838 dle_func_en(rtwdev, false);
1839 dle_clk_en(rtwdev, true);
1841 ret = dle_mix_cfg(rtwdev, cfg);
1843 rtw89_err(rtwdev, "[ERR] dle mix cfg\n");
1846 dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu);
1848 dle_func_en(rtwdev, true);
1852 2000, false, rtwdev, R_AX_WDE_INI_STATUS);
1854 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n");
1860 2000, false, rtwdev, R_AX_PLE_INI_STATUS);
1862 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n");
1868 dle_func_en(rtwdev, false);
1869 rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n",
1870 rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS));
1871 rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n",
1872 rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS));
1877 static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx,
1886 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size);
1887 rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN);
1892 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND);
1893 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size);
1898 static bool is_qta_poh(struct rtw89_dev *rtwdev)
1900 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE;
1903 static int preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx,
1906 const struct rtw89_chip_info *chip = rtwdev->chip;
1909 chip->chip_id == RTL8851B || !is_qta_poh(rtwdev))
1912 return preload_init_set(rtwdev, mac_idx, mode);
1915 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev)
1933 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0);
1941 static void _patch_ss2f_path(struct rtw89_dev *rtwdev)
1943 const struct rtw89_chip_info *chip = rtwdev->chip;
1949 rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK,
1953 static int sta_sch_init(struct rtw89_dev *rtwdev)
1959 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
1963 val = rtw89_read8(rtwdev, R_AX_SS_CTRL);
1965 rtw89_write8(rtwdev, R_AX_SS_CTRL, val);
1968 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL);
1970 rtw89_err(rtwdev, "[ERR]STA scheduler init\n");
1974 rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG);
1975 rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN);
1977 _patch_ss2f_path(rtwdev);
1982 static int mpdu_proc_init(struct rtw89_dev *rtwdev)
1986 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
1990 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD);
1991 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD);
1992 rtw89_write32_set(rtwdev, R_AX_MPDU_PROC,
1994 rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL);
1999 static int sec_eng_init(struct rtw89_dev *rtwdev)
2001 const struct rtw89_chip_info *chip = rtwdev->chip;
2005 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
2009 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL);
2018 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val);
2021 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC);
2025 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val);
2028 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1,
2034 static int dmac_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2038 ret = dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID);
2040 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret);
2044 ret = preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode);
2046 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret);
2050 ret = hfc_init(rtwdev, true, true, true);
2052 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret);
2056 ret = sta_sch_init(rtwdev);
2058 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret);
2062 ret = mpdu_proc_init(rtwdev);
2064 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret);
2068 ret = sec_eng_init(rtwdev);
2070 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret);
2077 static int addr_cam_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2083 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2087 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_ADDR_CAM_CTRL, mac_idx);
2089 val = rtw89_read32(rtwdev, reg);
2092 rtw89_write32(rtwdev, reg, val);
2095 1, TRXCFG_WAIT_CNT, false, rtwdev, reg);
2097 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n");
2104 static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2110 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2114 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_1, mac_idx);
2115 if (rtwdev->chip->chip_id == RTL8852C)
2116 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK,
2119 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK,
2122 if (rtwdev->chip->chip_id == RTL8852B || rtwdev->chip->chip_id == RTL8851B) {
2123 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCH_EXT_CTRL, mac_idx);
2124 rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV);
2127 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CFG_0, mac_idx);
2128 rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN);
2130 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_0, mac_idx);
2131 if (rtwdev->chip->chip_id == RTL8852C) {
2132 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL,
2135 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK,
2138 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK,
2145 int rtw89_mac_typ_fltr_opt(struct rtw89_dev *rtwdev,
2164 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n");
2170 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MGNT_FLTR, mac_idx);
2173 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTRL_FLTR, mac_idx);
2176 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DATA_FLTR, mac_idx);
2179 rtw89_err(rtwdev, "[ERR]set rx filter type err\n");
2182 rtw89_write32(rtwdev, reg, val);
2187 static int rx_fltr_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2192 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2197 ret = rtw89_mac_typ_fltr_opt(rtwdev, i, RTW89_FWD_TO_HOST,
2202 mac_ftlr = rtwdev->hal.rx_fltr;
2207 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx),
2209 rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx),
2215 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx)
2226 switch (rtwdev->chip->chip_id) {
2229 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx);
2230 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav;
2231 rtw89_write32(rtwdev, reg, val32);
2233 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx);
2234 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca;
2235 rtw89_write32(rtwdev, reg, val32);
2238 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx);
2239 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav;
2240 rtw89_write32(rtwdev, reg, val32);
2242 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx);
2243 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca;
2244 rtw89_write32(rtwdev, reg, val32);
2249 static int cca_ctrl_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2254 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2258 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CONTROL, mac_idx);
2259 val = rtw89_read32(rtwdev, reg);
2274 rtw89_write32(rtwdev, reg, val);
2276 _patch_dis_resp_chk(rtwdev, mac_idx);
2281 static int nav_ctrl_init(struct rtw89_dev *rtwdev)
2283 rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN |
2286 rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS);
2291 static int spatial_reuse_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2296 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2299 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_SR_CTRL, mac_idx);
2300 rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN);
2305 static int tmac_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2310 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2314 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MAC_LOOPBACK, mac_idx);
2315 rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN);
2317 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TCR0, mac_idx);
2318 rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD);
2320 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXD_FIFO_CTRL, mac_idx);
2321 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE);
2322 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE);
2327 static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2329 const struct rtw89_chip_info *chip = rtwdev->chip;
2334 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2338 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx);
2339 val = rtw89_read32(rtwdev, reg);
2343 switch (rtwdev->chip->chip_id) {
2356 rtw89_write32(rtwdev, reg, val);
2358 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, mac_idx);
2359 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN);
2361 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->ref_rate.addr, mac_idx);
2362 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data);
2363 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->rsc.addr, mac_idx);
2364 rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data);
2369 static void rst_bacam(struct rtw89_dev *rtwdev)
2374 rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK,
2379 rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK);
2381 rtw89_warn(rtwdev, "failed to reset BA CAM\n");
2384 static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2395 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2400 rst_bacam(rtwdev);
2402 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RESPBA_CAM_CTRL, mac_idx);
2403 rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL);
2405 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx);
2406 val = rtw89_read16(rtwdev, reg);
2411 rtw89_write16(rtwdev, reg, val);
2413 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx);
2414 rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1);
2416 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx);
2418 rx_qta = rtwdev->mac.dle_info.c0_rx_qta;
2420 rx_qta = rtwdev->mac.dle_info.c1_rx_qta;
2422 rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size;
2425 rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len);
2427 if (rtwdev->chip->chip_id == RTL8852A &&
2428 rtwdev->hal.cv == CHIP_CBV) {
2429 rtw89_write16_mask(rtwdev,
2430 rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx),
2432 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx),
2436 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx);
2437 rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK);
2442 static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2444 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2448 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2452 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx);
2453 val = rtw89_read32(rtwdev, reg);
2457 rtw89_write32(rtwdev, reg, val);
2460 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_RRSR1, mac_idx);
2461 rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN);
2467 static bool is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode)
2471 cfg = get_dle_mem_cfg(rtwdev, mode);
2473 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n");
2480 static int ptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2485 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2489 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) {
2490 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SIFS_SETTING, mac_idx);
2491 val = rtw89_read32(rtwdev, reg);
2497 rtw89_write32(rtwdev, reg, val);
2499 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_FSM_MON, mac_idx);
2500 val = rtw89_read32(rtwdev, reg);
2503 rtw89_write32(rtwdev, reg, val);
2507 rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0,
2509 rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0,
2513 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL,
2516 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1,
2523 static int cmac_dma_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2525 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2532 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2536 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXDMA_CTRL_0, mac_idx);
2537 rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE);
2542 static int cmac_init(struct rtw89_dev *rtwdev, u8 mac_idx)
2546 ret = scheduler_init(rtwdev, mac_idx);
2548 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret);
2552 ret = addr_cam_init(rtwdev, mac_idx);
2554 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx,
2559 ret = rx_fltr_init(rtwdev, mac_idx);
2561 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx,
2566 ret = cca_ctrl_init(rtwdev, mac_idx);
2568 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx,
2573 ret = nav_ctrl_init(rtwdev);
2575 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx,
2580 ret = spatial_reuse_init(rtwdev, mac_idx);
2582 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n",
2587 ret = tmac_init(rtwdev, mac_idx);
2589 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret);
2593 ret = trxptcl_init(rtwdev, mac_idx);
2595 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret);
2599 ret = rmac_init(rtwdev, mac_idx);
2601 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret);
2605 ret = cmac_com_init(rtwdev, mac_idx);
2607 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret);
2611 ret = ptcl_init(rtwdev, mac_idx);
2613 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret);
2617 ret = cmac_dma_init(rtwdev, mac_idx);
2619 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret);
2626 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev,
2635 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info);
2645 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev)
2647 struct rtw89_efuse *efuse = &rtwdev->efuse;
2648 struct rtw89_hal *hal = &rtwdev->hal;
2649 const struct rtw89_chip_info *chip = rtwdev->chip;
2658 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info);
2689 rtw89_debug(rtwdev, RTW89_DBG_FW,
2693 rtw89_debug(rtwdev, RTW89_DBG_FW,
2696 rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity);
2697 rtw89_debug(rtwdev, RTW89_DBG_FW, "Antenna diversity=%d\n", hal->ant_diversity);
2702 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band,
2717 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info);
2727 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx,
2730 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx);
2734 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2738 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags))
2739 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx,
2742 val = rtw89_read16(rtwdev, reg);
2744 rtw89_write16(rtwdev, reg, val);
2749 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx,
2752 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx);
2756 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
2760 val = rtw89_read32(rtwdev, reg);
2762 rtw89_write32(rtwdev, reg, val);
2767 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
2772 *tx_en = rtw89_read16(rtwdev,
2773 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx));
2777 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0,
2783 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx,
2789 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx,
2795 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0,
2808 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx,
2813 *tx_en = rtw89_read32(rtwdev,
2814 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx));
2818 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0,
2824 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx,
2830 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx,
2836 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0,
2849 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)
2853 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK);
2861 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)
2865 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en,
2874 int rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id)
2882 rtw89_write32(rtwdev, reg, val);
2887 1, 2000, false, rtwdev, reg);
2898 int rtw89_mac_set_cpuio(struct rtw89_dev *rtwdev,
2912 rtw89_write32(rtwdev, reg, val);
2924 rtw89_write32(rtwdev, reg, val);
2935 rtw89_write32(rtwdev, reg, val);
2940 1, 2000, false, rtwdev, reg);
2951 static int dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode)
2958 cfg = get_dle_mem_cfg(rtwdev, mode);
2960 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n");
2965 dle_expected_used_size(rtwdev, mode)) {
2966 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n");
2970 dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU);
2972 ret = rtw89_mac_dle_buf_req(rtwdev, 0x20, true, &pkt_id);
2974 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n");
2984 ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, true);
2986 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n");
2990 ret = rtw89_mac_dle_buf_req(rtwdev, 0x20, false, &pkt_id);
2992 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n");
3002 ret = rtw89_mac_set_cpuio(rtwdev, &ctrl_para, false);
3004 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n");
3011 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx)
3017 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
3021 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_TX_CTN_SEL, mac_idx);
3027 false, rtwdev, reg);
3034 static int band1_enable(struct rtw89_dev *rtwdev)
3041 ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL);
3043 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret);
3048 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4);
3049 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4);
3050 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX);
3051 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX);
3054 ret = band_idle_ck_b(rtwdev, 0);
3056 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret);
3060 ret = dle_quota_change(rtwdev, rtwdev->mac.qta_mode);
3062 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret);
3067 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]);
3068 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]);
3071 ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en);
3073 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret);
3077 ret = cmac_func_en(rtwdev, 1, true);
3079 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret);
3083 ret = cmac_init(rtwdev, 1);
3085 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret);
3089 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND,
3095 static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev)
3097 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3099 rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR);
3100 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set);
3103 static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev)
3105 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3107 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set);
3110 static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev)
3112 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3113 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3115 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR,
3122 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR,
3127 rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR,
3130 rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR,
3134 rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR,
3138 static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev)
3140 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3142 rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR,
3146 rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR,
3150 static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev)
3152 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3154 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg,
3156 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg,
3158 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg,
3160 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg,
3164 static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev)
3166 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3168 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr);
3169 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set);
3172 static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev)
3174 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3176 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr);
3177 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set);
3180 static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev)
3182 rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR,
3186 static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev)
3188 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3190 rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR,
3192 rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR,
3194 rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR,
3196 rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR,
3198 rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR,
3200 rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR,
3204 static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev)
3206 rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR);
3207 rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET);
3210 static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev)
3212 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3214 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg,
3216 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg,
3218 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg,
3220 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg,
3222 rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR);
3225 static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
3229 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCHEDULE_ERR_IMR, mac_idx);
3230 rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN |
3232 rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN);
3235 static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
3237 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3240 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_IMR0, mac_idx);
3241 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr);
3242 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set);
3245 static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
3247 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3248 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3251 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_0_reg, mac_idx);
3252 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr);
3253 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set);
3256 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_1_reg, mac_idx);
3257 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr);
3258 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set);
3262 static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
3264 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3267 reg = rtw89_mac_reg_by_idx(rtwdev, imr->phy_intf_imr_reg, mac_idx);
3268 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr);
3269 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set);
3272 static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
3274 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3277 reg = rtw89_mac_reg_by_idx(rtwdev, imr->rmac_imr_reg, mac_idx);
3278 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr);
3279 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set);
3282 static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx)
3284 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3287 reg = rtw89_mac_reg_by_idx(rtwdev, imr->tmac_imr_reg, mac_idx);
3288 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr);
3289 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set);
3292 static int rtw89_mac_enable_imr(struct rtw89_dev *rtwdev, u8 mac_idx,
3297 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel);
3299 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n",
3305 rtw89_wdrls_imr_enable(rtwdev);
3306 rtw89_wsec_imr_enable(rtwdev);
3307 rtw89_mpdu_trx_imr_enable(rtwdev);
3308 rtw89_sta_sch_imr_enable(rtwdev);
3309 rtw89_txpktctl_imr_enable(rtwdev);
3310 rtw89_wde_imr_enable(rtwdev);
3311 rtw89_ple_imr_enable(rtwdev);
3312 rtw89_pktin_imr_enable(rtwdev);
3313 rtw89_dispatcher_imr_enable(rtwdev);
3314 rtw89_cpuio_imr_enable(rtwdev);
3315 rtw89_bbrpt_imr_enable(rtwdev);
3317 rtw89_scheduler_imr_enable(rtwdev, mac_idx);
3318 rtw89_ptcl_imr_enable(rtwdev, mac_idx);
3319 rtw89_cdma_imr_enable(rtwdev, mac_idx);
3320 rtw89_phy_intf_imr_enable(rtwdev, mac_idx);
3321 rtw89_rmac_imr_enable(rtwdev, mac_idx);
3322 rtw89_tmac_imr_enable(rtwdev, mac_idx);
3330 static void rtw89_mac_err_imr_ctrl(struct rtw89_dev *rtwdev, bool en)
3332 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3334 rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR,
3336 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR,
3338 if (chip_id != RTL8852B && rtwdev->mac.dle_info.c1_rx_qta)
3339 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1,
3343 static int rtw89_mac_dbcc_enable(struct rtw89_dev *rtwdev, bool enable)
3348 ret = band1_enable(rtwdev);
3350 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret);
3354 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL);
3356 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret);
3360 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n");
3367 static int set_host_rpr(struct rtw89_dev *rtwdev)
3369 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) {
3370 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG,
3372 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0,
3375 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG,
3377 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0,
3381 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30);
3382 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255);
3387 static int rtw89_mac_trx_init(struct rtw89_dev *rtwdev)
3389 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode;
3392 ret = dmac_init(rtwdev, 0);
3394 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret);
3398 ret = cmac_init(rtwdev, 0);
3400 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret);
3404 if (is_qta_dbcc(rtwdev, qta_mode)) {
3405 ret = rtw89_mac_dbcc_enable(rtwdev, true);
3407 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret);
3412 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL);
3414 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret);
3418 ret = rtw89_mac_enable_imr(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL);
3420 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret);
3424 rtw89_mac_err_imr_ctrl(rtwdev, true);
3426 ret = set_host_rpr(rtwdev);
3428 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret);
3435 static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev)
3437 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3441 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN);
3442 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN);
3446 rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL,
3449 val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL);
3452 rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL);
3455 void rtw89_mac_disable_cpu(struct rtw89_dev *rtwdev)
3457 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags);
3459 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN);
3460 rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN |
3462 rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN);
3464 rtw89_disable_fw_watchdog(rtwdev);
3466 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
3467 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
3470 int rtw89_mac_enable_cpu(struct rtw89_dev *rtwdev, u8 boot_reason, bool dlfw)
3475 if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN)
3478 rtw89_write32(rtwdev, R_AX_UDM1, 0);
3479 rtw89_write32(rtwdev, R_AX_UDM2, 0);
3480 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0);
3481 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0);
3482 rtw89_write32(rtwdev, R_AX_HALT_H2C, 0);
3483 rtw89_write32(rtwdev, R_AX_HALT_C2H, 0);
3485 rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN);
3487 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL);
3495 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val);
3497 if (rtwdev->chip->chip_id == RTL8852B)
3498 rtw89_write32_mask(rtwdev, R_AX_SEC_CTRL,
3501 rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK,
3503 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN);
3508 ret = rtw89_fw_check_rdy(rtwdev);
3516 static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev)
3518 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
3528 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val);
3534 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val);
3539 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1);
3543 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val);
3545 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1,
3550 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11);
3551 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN);
3554 ret = dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode);
3556 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret);
3560 ret = hfc_init(rtwdev, true, false, true);
3562 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret);
3569 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
3571 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN,
3573 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL,
3576 rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE);
3582 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
3584 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN,
3586 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL,
3589 rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE);
3595 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev)
3599 ret = rtw89_mac_power_switch(rtwdev, true);
3601 rtw89_mac_power_switch(rtwdev, false);
3602 ret = rtw89_mac_power_switch(rtwdev, true);
3607 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true);
3609 ret = rtw89_mac_dmac_pre_init(rtwdev);
3613 if (rtwdev->hci.ops->mac_pre_init) {
3614 ret = rtwdev->hci.ops->mac_pre_init(rtwdev);
3619 ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL);
3626 int rtw89_mac_init(struct rtw89_dev *rtwdev)
3630 ret = rtw89_mac_partial_init(rtwdev);
3634 ret = rtw89_chip_enable_bb_rf(rtwdev);
3638 ret = rtw89_mac_sys_init(rtwdev);
3642 ret = rtw89_mac_trx_init(rtwdev);
3646 if (rtwdev->hci.ops->mac_post_init) {
3647 ret = rtwdev->hci.ops->mac_post_init(rtwdev);
3652 rtw89_fw_send_all_early_h2c(rtwdev);
3653 rtw89_fw_h2c_set_ofld_cfg(rtwdev);
3657 rtw89_mac_power_switch(rtwdev, false);
3662 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid)
3666 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX)
3670 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR,
3672 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0);
3676 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid)
3678 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX)
3681 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR,
3683 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4);
3684 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004);
3685 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0);
3686 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0);
3687 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0);
3688 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B);
3689 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0);
3690 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109);
3693 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause)
3702 if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) &&
3703 !test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
3706 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL);
3710 rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause);
3742 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev,
3748 if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN))
3751 rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK);
3752 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1);
3753 rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK);
3754 rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK);
3758 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN |
3760 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST);
3761 rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0);
3764 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev,
3770 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN);
3772 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN);
3775 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev,
3781 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN);
3783 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN);
3786 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev,
3791 rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK,
3795 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev,
3803 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits);
3805 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits);
3808 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev,
3817 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit);
3819 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit);
3822 static void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev,
3830 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN);
3832 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN);
3835 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev,
3841 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN);
3843 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN);
3846 static void rtw89_mac_port_cfg_tx_sw_by_nettype(struct rtw89_dev *rtwdev,
3852 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif, en);
3855 void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en)
3859 rtw89_for_each_rtwvif(rtwdev, rtwvif)
3861 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif, en);
3864 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev,
3871 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK,
3875 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev,
3887 reg = rtw89_mac_reg_by_idx(rtwdev, hiq_win_addr[port], rtwvif->mac_idx);
3888 rtw89_write8(rtwdev, reg, win);
3891 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev,
3898 addr = rtw89_mac_reg_by_idx(rtwdev, R_AX_MD_TSFT_STMP_CTL, rtwvif->mac_idx);
3899 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE);
3901 rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK,
3905 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev,
3910 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib,
3914 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev,
3919 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib,
3923 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev,
3928 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area,
3932 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev,
3937 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early,
3941 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev,
3957 reg = rtw89_mac_reg_by_idx(rtwdev, reg_base, rtwvif->mac_idx);
3958 rtw89_write32_mask(rtwdev, reg, masks[port], bss_color);
3961 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev,
3971 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MBSSID_CTRL, rtwvif->mac_idx);
3972 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK);
3976 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev,
3983 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MBSSID_DROP_0, rtwvif->mac_idx);
3984 val = rtw89_read32(rtwdev, reg);
3988 rtw89_write32(rtwdev, reg, val);
3991 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev,
3997 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg,
4000 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg,
4004 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev,
4009 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK,
4013 static void rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev *rtwdev,
4019 if (rtwdev->chip->chip_id != RTL8852C)
4029 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_shift,
4033 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev,
4041 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PORT0_TSF_SYNC + rtwvif->port * 4,
4044 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port);
4045 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val);
4046 rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW);
4049 static void rtw89_mac_port_tsf_sync_rand(struct rtw89_dev *rtwdev,
4059 rtw89_mac_port_tsf_sync(rtwdev, rtwvif, rtwvif_src,
4065 static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev)
4071 rtw89_for_each_rtwvif(rtwdev, tmp) {
4083 rtw89_for_each_rtwvif(rtwdev, tmp)
4084 rtw89_mac_port_tsf_sync_rand(rtwdev, tmp, src, offset, &n_offset);
4087 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
4091 ret = rtw89_mac_port_update(rtwdev, rtwvif);
4095 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id);
4096 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id);
4098 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif->mac_id, false);
4102 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_CREATE);
4106 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, NULL, true);
4110 ret = rtw89_cam_init(rtwdev, rtwvif);
4114 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL);
4118 ret = rtw89_fw_h2c_default_cmac_tbl(rtwdev, rtwvif);
4125 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
4129 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_REMOVE);
4133 rtw89_cam_deinit(rtwdev, rtwvif);
4135 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL);
4142 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
4149 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif);
4150 rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false);
4151 rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false);
4152 rtw89_mac_port_cfg_net_type(rtwdev, rtwvif);
4153 rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif);
4154 rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif);
4155 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif);
4156 rtw89_mac_port_cfg_tx_sw_by_nettype(rtwdev, rtwvif);
4157 rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif);
4158 rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif);
4159 rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif);
4160 rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif);
4161 rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif);
4162 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif);
4163 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif);
4164 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif);
4165 rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif);
4166 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif);
4167 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif);
4168 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, true);
4169 rtw89_mac_port_tsf_resync_all(rtwdev);
4171 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif);
4176 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4183 ret = rtw89_mac_check_mac_en(rtwdev, rtwvif->mac_idx, RTW89_CMAC_SEL);
4187 tsf_low = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_l);
4188 tsf_high = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_h);
4213 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev,
4217 struct ieee80211_hw *hw = rtwdev->hw;
4231 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, rtwvif->mac_idx);
4233 rtw89_write32_clr(rtwdev, reg, B_AX_RXTRIG_RU26_DIS);
4235 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_RU26_DIS);
4238 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
4240 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, false);
4243 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
4247 rtwvif->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map,
4252 ret = rtw89_mac_vif_init(rtwdev, rtwvif);
4259 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id);
4264 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
4268 ret = rtw89_mac_vif_deinit(rtwdev, rtwvif);
4269 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwvif->mac_id);
4275 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
4279 static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel)
4281 const struct rtw89_chan *op = &rtwdev->scan_info.op_chan;
4287 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
4290 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif;
4294 u32 last_chan = rtwdev->scan_info.last_chan_idx;
4308 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ)))
4311 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN,
4317 if (rtw89_is_op_chan(rtwdev, band, chan)) {
4318 rtw89_mac_enable_beacon_for_ap_vifs(rtwdev, false);
4319 ieee80211_stop_queues(rtwdev->hw);
4325 ret = rtw89_hw_scan_offload(rtwdev, vif, true);
4327 rtw89_hw_scan_abort(rtwdev, vif);
4328 rtw89_warn(rtwdev, "HW scan failed: %d\n", ret);
4331 rtw89_hw_scan_complete(rtwdev, vif, false);
4335 if (rtw89_is_op_chan(rtwdev, band, chan)) {
4336 rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx,
4337 &rtwdev->scan_info.op_chan);
4338 rtw89_mac_enable_beacon_for_ap_vifs(rtwdev, true);
4339 ieee80211_wake_queues(rtwdev->hw);
4343 rtw89_assign_entity_chan(rtwdev, rtwvif->sub_entity_idx,
4353 rtw89_mac_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4371 rtw89_debug(rtwdev, RTW89_DBG_FW,
4377 if (!rtwdev->scanning && !rtwvif->offchan)
4380 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, true);
4401 rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
4406 rtw89_for_each_rtwvif(rtwdev, rtwvif)
4407 rtw89_mac_bcn_fltr_rpt(rtwdev, rtwvif, c2h);
4411 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
4415 rtw89_debug(rtwdev, RTW89_DBG_FW,
4424 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len)
4427 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait;
4438 rtw89_debug(rtwdev, RTW89_DBG_FW,
4465 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
4467 rtw89_fw_log_dump(rtwdev, c2h->data, len);
4471 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
4476 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h,
4479 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait;
4488 rtw89_debug(rtwdev, RTW89_DBG_FW, "pkt ofld rsp: id %d op %d len %d\n",
4498 rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
4504 rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
4521 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
4526 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
4531 rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
4554 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
4559 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
4568 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data);
4572 rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
4587 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
4593 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data);
4597 rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
4649 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
4654 rtw89_debug(rtwdev, RTW89_DBG_CHAN,
4663 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data);
4667 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev,
4680 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev,
4689 void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev,
4697 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func)
4722 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
4725 void (*handler)(struct rtw89_dev *rtwdev,
4744 rtw89_info(rtwdev, "c2h class %d not support\n", class);
4748 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class,
4752 handler(rtwdev, skb, len);
4755 bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev,
4759 const struct rtw89_dle_mem *dle_mem = rtwdev->chip->dle_mem;
4761 u32 addr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx);
4764 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n",
4771 rtw89_err(rtwdev,
4781 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n",
4788 int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)
4790 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PPDU_STAT, mac_idx);
4793 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
4798 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN);
4802 rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN |
4806 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK,
4813 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx)
4821 struct ieee80211_hw *hw = rtwdev->hw;
4837 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AGG_LEN_HT_0, mac_idx);
4838 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th);
4839 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th);
4842 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop)
4847 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
4851 10000, 200000, false, rtwdev);
4852 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning))
4853 rtw89_info(rtwdev, "timed out to flush queues\n");
4856 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex)
4863 rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT);
4864 if (rtwdev->chip->chip_id != RTL8851B)
4865 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN);
4866 rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8);
4867 rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK);
4868 rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16);
4869 if (rtwdev->chip->chip_id != RTL8851B)
4870 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24);
4872 val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0);
4874 rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16);
4876 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32);
4878 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n");
4882 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32);
4884 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n");
4890 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG);
4893 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val);
4895 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE);
4896 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE);
4898 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5);
4901 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val);
4904 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG);
4907 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val);
4909 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE);
4917 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16);
4919 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE);
4927 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1);
4929 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val);
4932 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1);
4934 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val);
4937 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1);
4939 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val);
4949 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev,
4952 rtw89_write32_set(rtwdev, R_AX_BTC_CFG,
4954 rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN);
4955 rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN);
4956 rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN);
4960 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK,
4962 rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1,
4966 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK,
4977 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev,
5006 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val);
5008 rtw89_err(rtwdev, "Write LTE fail!\n");
5016 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev,
5057 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val);
5063 int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt)
5069 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL);
5073 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, plt->band);
5083 rtw89_write16(rtwdev, reg, val);
5088 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val)
5092 fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD);
5095 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
5103 rtw89_write32(rtwdev, R_AX_SCOREBOARD, val);
5107 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev)
5109 return rtw89_read32(rtwdev, R_AX_SCOREBOARD);
5112 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl)
5114 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3);
5117 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val);
5123 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl)
5125 struct rtw89_btc *btc = &rtwdev->btc;
5140 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt);
5144 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev)
5146 const struct rtw89_chip_info *chip = rtwdev->chip;
5152 val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3,
5158 u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band)
5163 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, band);
5164 cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK);
5165 rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST);
5170 static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx,
5175 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep);
5176 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx);
5178 set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags);
5179 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK,
5182 clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags);
5183 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK,
5188 static void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en)
5194 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en);
5195 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx);
5197 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags);
5198 rtw89_write32_set(rtwdev, reg, mask);
5200 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags);
5201 rtw89_write32_clr(rtwdev, reg, mask);
5205 static int rtw89_mac_init_bfee(struct rtw89_dev *rtwdev, u8 mac_idx)
5211 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
5217 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMER_CTRL_0, mac_idx);
5218 rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN);
5220 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx);
5221 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP);
5223 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx);
5225 rtw89_write32(rtwdev, reg, val32);
5226 rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true);
5227 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true);
5229 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
5230 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL |
5234 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx);
5235 rtw89_write32(rtwdev, reg,
5240 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CSIRPT_OPTION, mac_idx);
5241 rtw89_write32_set(rtwdev, reg,
5247 static int rtw89_mac_set_csi_para_reg(struct rtw89_dev *rtwdev,
5261 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
5284 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
5285 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL);
5296 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
5298 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx);
5300 rtw89_write16(rtwdev, reg, val);
5305 static int rtw89_mac_csi_rrsc(struct rtw89_dev *rtwdev,
5315 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
5334 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx);
5335 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL);
5336 rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN);
5337 rtw89_write32(rtwdev,
5338 rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx),
5344 void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
5350 rtw89_debug(rtwdev, RTW89_DBG_BF,
5352 rtw89_mac_init_bfee(rtwdev, rtwvif->mac_idx);
5353 rtw89_mac_set_csi_para_reg(rtwdev, vif, sta);
5354 rtw89_mac_csi_rrsc(rtwdev, vif, sta);
5358 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
5363 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false);
5366 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
5373 rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n");
5376 rtw89_write32(rtwdev,
5377 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN0, mac_idx),
5379 rtw89_write32(rtwdev,
5380 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN1, mac_idx),
5384 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION0, mac_idx),
5386 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION1, mac_idx),
5388 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION2, mac_idx),
5390 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION3, mac_idx),
5395 struct rtw89_dev *rtwdev;
5415 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev,
5420 data.rtwdev = rtwdev;
5423 ieee80211_iterate_stations_atomic(rtwdev->hw,
5427 rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count);
5429 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags);
5431 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags);
5434 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev)
5436 struct rtw89_traffic_stats *stats = &rtwdev->stats;
5439 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags);
5443 old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags);
5449 rtw89_for_each_rtwvif(rtwdev, rtwvif)
5450 rtw89_mac_bfee_standby_timer(rtwdev, rtwvif->mac_idx,
5457 rtw89_for_each_rtwvif(rtwdev, rtwvif)
5458 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en);
5462 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
5473 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta);
5475 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
5477 rtw89_warn(rtwdev, "failed to check cmac in set txtime\n");
5481 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx);
5482 rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK,
5489 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
5496 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time);
5498 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time);
5505 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
5515 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
5517 rtw89_warn(rtwdev, "failed to check cmac in tx_time\n");
5521 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx);
5522 *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5;
5528 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev,
5538 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta);
5540 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta);
5547 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev,
5557 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
5559 rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n");
5563 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXCNT, mac_idx);
5564 *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK);
5570 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev,
5578 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL);
5582 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MUEDCA_EN, mac_idx);
5584 rtw89_write16_set(rtwdev, reg, set);
5586 rtw89_write16_clr(rtwdev, reg, set);
5591 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask)
5601 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32);
5604 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL);
5606 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n",
5615 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val)
5625 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32);
5628 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL);
5630 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset);
5634 *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1);
5641 void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta)
5661 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms);
5669 struct rtw89_dev *rtwdev = rtwvif->rtwdev;
5675 rtw89_mac_pkt_drop_sta(rtwdev, rtwsta);
5678 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
5680 ieee80211_iterate_stations_atomic(rtwdev->hw,
5685 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev,
5697 50000, false, rtwdev);
5698 if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw))
5699 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms);