Lines Matching defs:val
40 u32 val, enum rtw89_mac_mem_sel sel)
46 rtw89_write32(rtwdev, mac->indir_access_addr, val);
62 u32 val, r_val;
66 val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN);
69 val = B_AX_CMAC_EN;
72 val = B_AX_CMAC1_FEN;
77 (val & r_val) != val)
83 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val)
93 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val);
99 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val)
110 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA);
119 u32 val;
144 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE),
216 u32 val, not_empty, i;
253 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG);
255 FIELD_GET(B_AX_PLE_Q6_MIN_SIZE_MASK, val));
257 FIELD_GET(B_AX_PLE_Q6_MAX_SIZE_MASK, val));
829 u32 val = 0;
842 val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) |
845 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val);
857 u32 val;
867 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4);
868 info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK);
870 info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK);
882 u32 val;
893 val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) |
895 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val);
897 val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK);
898 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val);
911 u32 val;
918 val = rtw89_read32(rtwdev, regs->pub_page_info1);
919 info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK);
920 info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK);
921 val = rtw89_read32(rtwdev, regs->pub_page_info3);
922 info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK);
923 info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK);
931 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl);
932 param->en = val & B_AX_HCI_FC_EN ? 1 : 0;
933 param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0;
934 param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK);
936 u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK);
938 u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK);
940 u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK);
942 u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK);
944 val = rtw89_read32(rtwdev, regs->ch_page_ctrl);
945 prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK);
946 prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK);
948 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2);
949 pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK);
951 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1);
952 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK);
953 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK);
955 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2);
956 pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK);
958 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1);
959 pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK);
960 pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK);
975 u32 val;
977 val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK);
978 rtw89_write32(rtwdev, regs->ch_page_ctrl, val);
992 u32 val;
994 val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) |
996 rtw89_write32(rtwdev, regs->ch_page_ctrl, val);
998 val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK);
999 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val);
1001 val = u32_encode_bits(prec_cfg->wp_ch07_prec,
1005 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val);
1007 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl),
1009 val = u32_replace_bits(val, prec_cfg->ch011_full_cond,
1011 val = u32_replace_bits(val, prec_cfg->h2c_full_cond,
1013 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond,
1015 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond,
1017 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val);
1025 u32 val;
1027 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl);
1030 val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN);
1031 val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) :
1032 (val & ~B_AX_HCI_FC_CH12_EN);
1033 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val);
1093 u8 val = 0;
1098 ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk),
1106 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val);
1116 u8 val;
1130 val = rtw89_read8(rtwdev, addr);
1131 val &= ~(cur_cfg->msk);
1132 val |= (cur_cfg->val & cur_cfg->msk);
1134 rtw89_write8(rtwdev, addr, val);
1141 if (cur_cfg->val == PWR_DELAY_US)
1311 u8 val;
1324 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK);
1325 if (on && val == PWR_ACT) {
1635 u32 val = B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN;
1639 val |= B_AX_AXIDMA_CLK_EN;
1640 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, val);
1642 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, val);
1649 u32 val;
1652 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG);
1658 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64,
1662 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128,
1670 val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK);
1671 val = u32_replace_bits(val, size_cfg->lnk_pge_num,
1673 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val);
1675 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG);
1686 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128,
1690 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256,
1695 val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK);
1696 val = u32_replace_bits(val, size_cfg->lnk_pge_num,
1698 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val);
1706 val = u32_encode_bits(_min_x, B_AX_ ## _module ## _MIN_SIZE_MASK) | \
1710 val); \
1722 u32 val;
1734 u32 val;
1755 u32 val;
1956 u8 val;
1963 val = rtw89_read8(rtwdev, R_AX_SS_CTRL);
1964 val |= B_AX_SS_EN;
1965 rtw89_write8(rtwdev, R_AX_SS_CTRL, val);
2002 u32 val = 0;
2009 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL);
2011 val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP);
2013 val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC);
2014 val |= (B_AX_MC_DEC | B_AX_BC_DEC);
2017 val &= ~B_AX_TX_PARTIAL_MODE;
2018 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val);
2021 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC);
2022 val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC);
2025 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val);
2079 u32 val, reg;
2089 val = rtw89_read32(rtwdev, reg);
2090 val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) |
2092 rtw89_write32(rtwdev, reg, val);
2108 u32 val;
2132 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL,
2134 if (!val)
2151 u32 val;
2155 val = RX_FLTR_FRAME_DROP;
2158 val = RX_FLTR_FRAME_TO_HOST;
2161 val = RX_FLTR_FRAME_TO_WLCPU;
2182 rtw89_write32(rtwdev, reg, val);
2251 u32 val, reg;
2259 val = rtw89_read32(rtwdev, reg);
2260 val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA |
2268 val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 |
2274 rtw89_write32(rtwdev, reg, val);
2331 u32 reg, val, sifs;
2339 val = rtw89_read32(rtwdev, reg);
2340 val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK;
2341 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK);
2354 val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK;
2355 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs);
2356 rtw89_write32(rtwdev, reg, val);
2393 u16 val;
2406 val = rtw89_read16(rtwdev, reg);
2407 val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO,
2409 val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO,
2411 rtw89_write16(rtwdev, reg, val);
2445 u32 val, reg;
2453 val = rtw89_read32(rtwdev, reg);
2454 val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK);
2455 val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK);
2456 val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK);
2457 rtw89_write32(rtwdev, reg, val);
2482 u32 val, reg;
2491 val = rtw89_read32(rtwdev, reg);
2492 val = u32_replace_bits(val, S_AX_CTS2S_TH_1K,
2494 val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B,
2496 val |= B_AX_HW_CTS2SELF_EN;
2497 rtw89_write32(rtwdev, reg, val);
2500 val = rtw89_read32(rtwdev, reg);
2501 val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK);
2502 val &= ~B_AX_PTCL_TX_ARB_TO_MODE;
2503 rtw89_write32(rtwdev, reg, val);
2731 u16 val;
2742 val = rtw89_read16(rtwdev, reg);
2743 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask);
2744 rtw89_write16(rtwdev, reg, val);
2753 u32 val;
2760 val = rtw89_read32(rtwdev, reg);
2761 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask);
2762 rtw89_write32(rtwdev, reg, val);
2876 u32 val, reg;
2880 val = buf_len;
2881 val |= B_AX_WD_BUF_REQ_EXEC;
2882 rtw89_write32(rtwdev, reg, val);
2886 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE,
2891 *pkt_id = FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val);
2901 u32 val, cmd_type, reg;
2907 val = 0;
2908 val = u32_replace_bits(val, ctrl_para->start_pktid,
2910 val = u32_replace_bits(val, ctrl_para->end_pktid,
2912 rtw89_write32(rtwdev, reg, val);
2915 val = 0;
2916 val = u32_replace_bits(val, ctrl_para->src_pid,
2918 val = u32_replace_bits(val, ctrl_para->src_qid,
2920 val = u32_replace_bits(val, ctrl_para->dst_pid,
2922 val = u32_replace_bits(val, ctrl_para->dst_qid,
2924 rtw89_write32(rtwdev, reg, val);
2927 val = 0;
2928 val = u32_replace_bits(val, cmd_type,
2930 val = u32_replace_bits(val, ctrl_para->macid,
2932 val = u32_replace_bits(val, ctrl_para->pkt_num,
2934 val |= B_AX_WD_CPUQ_OP_EXEC;
2935 rtw89_write32(rtwdev, reg, val);
2939 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE,
2946 ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val);
3015 u8 val;
3023 ret = read_poll_timeout(rtw89_read8, val,
3024 (val & B_AX_PTCL_TX_ON_STAT) == 0,
3472 u32 val;
3487 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL);
3488 val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY);
3489 val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE,
3493 val |= B_AX_WCPU_FWDL_EN;
3495 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val);
3519 u32 val;
3523 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN |
3526 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN |
3528 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val);
3531 val = B_AX_DISPATCHER_CLK_EN | B_AX_AXIDMA_CLK_EN;
3533 val = B_AX_DISPATCHER_CLK_EN;
3534 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val);
3539 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1);
3540 val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST);
3541 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B) |
3543 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val);
3981 u32 val;
3984 val = rtw89_read32(rtwdev, reg);
3985 val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port));
3987 val &= ~BIT(0);
3988 rtw89_write32(rtwdev, reg, val);
4017 u16 val;
4026 val = FIELD_PREP(B_AX_TBTT_SHIFT_OFST_MAG, 1) |
4030 B_AX_TBTT_SHIFT_OFST_MASK, val);
4038 u32 val, reg;
4040 val = RTW89_PORT_OFFSET_TU_TO_32US(offset_tu);
4045 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val);
4858 u8 val;
4890 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG);
4891 val &= ~B_AX_BTMODE_MASK;
4892 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3);
4893 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val);
4895 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE);
4896 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE);
4898 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5);
4899 val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK;
4900 val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE);
4901 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val);
4904 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG);
4905 val &= ~B_AX_BTMODE_MASK;
4906 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2);
4907 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val);
4927 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1);
4928 val = (val & ~BIT(2)) | BIT(1);
4929 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val);
4932 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1);
4933 val = val | BIT(1) | BIT(0);
4934 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val);
4937 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1);
4938 val = val & ~(BIT(2) | BIT(1));
4939 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val);
4980 u32 val = 0, ret;
4983 val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL;
4986 val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL;
4989 val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL;
4992 val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL;
4995 val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL;
4998 val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL;
5001 val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL;
5004 val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL;
5006 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val);
5019 u32 val = 0;
5022 val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL |
5025 val |= B_AX_WL_ACT_VAL;
5028 val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL |
5032 val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL |
5036 val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL |
5040 val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL |
5043 val |= B_AX_WL_ACT_VAL;
5046 val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL |
5050 val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL |
5054 val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL |
5057 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val);
5066 u16 val;
5074 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) |
5083 rtw89_write16(rtwdev, reg, val);
5088 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val)
5099 val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val);
5100 val = B_AX_TOGGLE |
5101 FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) |
5103 rtw89_write32(rtwdev, R_AX_SCOREBOARD, val);
5114 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3);
5116 val = wl ? val | BIT(2) : val & ~BIT(2);
5117 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val);
5147 u8 val = 0;
5152 val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3,
5155 return !!val;
5258 u16 val;
5287 val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) |
5300 rtw89_write16(rtwdev, reg, val);
5591 int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask)
5597 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) |
5606 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n",
5607 offset, val, mask);
5615 int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val)
5634 *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1);