Lines Matching defs:imr
652 u32 dmac_err, imr, isr;
662 imr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR);
666 ((isr & imr) & B_AX_B0_ISR_ERR_CMDPSR_FRZTO)) {
3097 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3100 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set);
3105 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3107 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set);
3113 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3128 imr->mpdu_tx_imr_set);
3135 imr->mpdu_rx_imr_set);
3140 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3147 imr->sta_sch_imr_set);
3152 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3154 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg,
3155 imr->txpktctl_imr_b0_clr);
3156 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg,
3157 imr->txpktctl_imr_b0_set);
3158 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg,
3159 imr->txpktctl_imr_b1_clr);
3160 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg,
3161 imr->txpktctl_imr_b1_set);
3166 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3168 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr);
3169 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set);
3174 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3176 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr);
3177 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set);
3188 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3191 imr->host_disp_imr_clr);
3193 imr->host_disp_imr_set);
3195 imr->cpu_disp_imr_clr);
3197 imr->cpu_disp_imr_set);
3199 imr->other_disp_imr_clr);
3201 imr->other_disp_imr_set);
3212 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3214 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg,
3216 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg,
3218 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg,
3219 imr->bbrpt_err_imr_set);
3220 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg,
3237 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3241 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr);
3242 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set);
3247 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3251 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_0_reg, mac_idx);
3252 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr);
3253 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set);
3256 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_1_reg, mac_idx);
3257 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr);
3258 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set);
3264 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3267 reg = rtw89_mac_reg_by_idx(rtwdev, imr->phy_intf_imr_reg, mac_idx);
3268 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr);
3269 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set);
3274 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3277 reg = rtw89_mac_reg_by_idx(rtwdev, imr->rmac_imr_reg, mac_idx);
3278 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr);
3279 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set);
3284 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info;
3287 reg = rtw89_mac_reg_by_idx(rtwdev, imr->tmac_imr_reg, mac_idx);
3288 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr);
3289 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set);