Lines Matching defs:addr
43 u32 addr = mac->mem_base_addrs[sel] + offset;
45 rtw89_write32(rtwdev, mac->filter_model_addr, addr);
53 u32 addr = mac->mem_base_addrs[sel] + offset;
55 rtw89_write32(rtwdev, mac->filter_model_addr, addr);
127 FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) |
134 FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) |
164 ctrl.addr = quota->qtaid;
184 ctrl.addr = qempty->grpsel;
233 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) |
1095 u32 addr = cfg->base == PWR_INTF_MSK_SDIO ?
1096 cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr;
1099 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr);
1105 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr);
1115 u32 addr;
1125 addr = cur_cfg->addr;
1128 addr |= SDIO_LOCAL_BASE_ADDR;
1130 val = rtw89_read8(rtwdev, addr);
1134 rtw89_write8(rtwdev, addr, val);
1142 udelay(cur_cfg->addr);
1144 fsleep(cur_cfg->addr * 1000);
2361 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->ref_rate.addr, mac_idx);
2363 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->rsc.addr, mac_idx);
3896 u32 addr;
3898 addr = rtw89_mac_reg_by_idx(rtwdev, R_AX_MD_TSFT_STMP_CTL, rtwvif->mac_idx);
3899 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE);
4761 u32 addr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx);
4763 if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR) {
4764 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n",
4765 addr);
4769 if (addr >= CMAC1_START_ADDR && addr <= CMAC1_END_ADDR)
4772 "[TXPWR] addr=0x%x but hw not enable\n",
4773 addr);
4777 *cr = addr;
4782 addr, phy_idx);