Lines Matching refs:info
2197 const struct rtw89_mac_dbg_port_info *info;
2205 info = &dbg_port_ptcl_c0;
2212 info = &dbg_port_ptcl_c1;
2219 info = &dbg_port_sch_c0;
2226 info = &dbg_port_sch_c1;
2233 info = &dbg_port_tmac_c0;
2250 info = &dbg_port_tmac_c1;
2267 info = &dbg_port_rmac_c0;
2289 info = &dbg_port_rmac_c1;
2311 info = &dbg_port_rmacst_c0;
2315 info = &dbg_port_rmacst_c1;
2319 info = &dbg_port_rmac_plcp_c0;
2323 info = &dbg_port_rmac_plcp_c1;
2327 info = &dbg_port_trxptcl_c0;
2339 info = &dbg_port_trxptcl_c1;
2351 info = &dbg_port_tx_infol_c0;
2358 info = &dbg_port_tx_infoh_c0;
2365 info = &dbg_port_tx_infol_c1;
2372 info = &dbg_port_tx_infoh_c1;
2379 info = &dbg_port_txtf_infol_c0;
2386 info = &dbg_port_txtf_infoh_c0;
2393 info = &dbg_port_txtf_infol_c1;
2400 info = &dbg_port_txtf_infoh_c1;
2407 info = &dbg_port_wde_bufmgn_freepg;
2411 info = &dbg_port_wde_bufmgn_quota;
2415 info = &dbg_port_wde_bufmgn_pagellt;
2419 info = &dbg_port_wde_bufmgn_pktinfo;
2423 info = &dbg_port_wde_quemgn_prepkt;
2427 info = &dbg_port_wde_quemgn_nxtpkt;
2431 info = &dbg_port_wde_quemgn_qlnktbl;
2435 info = &dbg_port_wde_quemgn_qempty;
2439 info = &dbg_port_ple_bufmgn_freepg;
2443 info = &dbg_port_ple_bufmgn_quota;
2447 info = &dbg_port_ple_bufmgn_pagellt;
2451 info = &dbg_port_ple_bufmgn_pktinfo;
2455 info = &dbg_port_ple_quemgn_prepkt;
2459 info = &dbg_port_ple_quemgn_nxtpkt;
2463 info = &dbg_port_ple_quemgn_qlnktbl;
2467 info = &dbg_port_ple_quemgn_qempty;
2471 info = &dbg_port_pktinfo;
2485 info = &dbg_port_dspt_hdt_tx0_5;
2487 rtw89_write16_mask(rtwdev, info->sel_addr,
2489 rtw89_write16_mask(rtwdev, info->sel_addr,
2494 info = &dbg_port_dspt_hdt_tx6;
2495 rtw89_write16_mask(rtwdev, info->sel_addr,
2497 rtw89_write16_mask(rtwdev, info->sel_addr,
2502 info = &dbg_port_dspt_hdt_tx7;
2503 rtw89_write16_mask(rtwdev, info->sel_addr,
2505 rtw89_write16_mask(rtwdev, info->sel_addr,
2510 info = &dbg_port_dspt_hdt_tx8;
2511 rtw89_write16_mask(rtwdev, info->sel_addr,
2513 rtw89_write16_mask(rtwdev, info->sel_addr,
2521 info = &dbg_port_dspt_hdt_tx9_C;
2523 rtw89_write16_mask(rtwdev, info->sel_addr,
2525 rtw89_write16_mask(rtwdev, info->sel_addr,
2530 info = &dbg_port_dspt_hdt_txD;
2531 rtw89_write16_mask(rtwdev, info->sel_addr,
2533 rtw89_write16_mask(rtwdev, info->sel_addr,
2538 info = &dbg_port_dspt_cdt_tx0;
2539 rtw89_write16_mask(rtwdev, info->sel_addr,
2541 rtw89_write16_mask(rtwdev, info->sel_addr,
2546 info = &dbg_port_dspt_cdt_tx1;
2547 rtw89_write16_mask(rtwdev, info->sel_addr,
2549 rtw89_write16_mask(rtwdev, info->sel_addr,
2554 info = &dbg_port_dspt_cdt_tx3;
2555 rtw89_write16_mask(rtwdev, info->sel_addr,
2557 rtw89_write16_mask(rtwdev, info->sel_addr,
2562 info = &dbg_port_dspt_cdt_tx4;
2563 rtw89_write16_mask(rtwdev, info->sel_addr,
2565 rtw89_write16_mask(rtwdev, info->sel_addr,
2573 info = &dbg_port_dspt_cdt_tx5_8;
2575 rtw89_write16_mask(rtwdev, info->sel_addr,
2577 rtw89_write16_mask(rtwdev, info->sel_addr,
2582 info = &dbg_port_dspt_cdt_tx9;
2583 rtw89_write16_mask(rtwdev, info->sel_addr,
2585 rtw89_write16_mask(rtwdev, info->sel_addr,
2592 info = &dbg_port_dspt_cdt_txA_C;
2594 rtw89_write16_mask(rtwdev, info->sel_addr,
2596 rtw89_write16_mask(rtwdev, info->sel_addr,
2601 info = &dbg_port_dspt_hdt_rx0;
2602 rtw89_write16_mask(rtwdev, info->sel_addr,
2604 rtw89_write16_mask(rtwdev, info->sel_addr,
2610 info = &dbg_port_dspt_hdt_rx1_2;
2612 rtw89_write16_mask(rtwdev, info->sel_addr,
2614 rtw89_write16_mask(rtwdev, info->sel_addr,
2619 info = &dbg_port_dspt_hdt_rx3;
2620 rtw89_write16_mask(rtwdev, info->sel_addr,
2622 rtw89_write16_mask(rtwdev, info->sel_addr,
2627 info = &dbg_port_dspt_hdt_rx4;
2628 rtw89_write16_mask(rtwdev, info->sel_addr,
2630 rtw89_write16_mask(rtwdev, info->sel_addr,
2635 info = &dbg_port_dspt_hdt_rx5;
2636 rtw89_write16_mask(rtwdev, info->sel_addr,
2638 rtw89_write16_mask(rtwdev, info->sel_addr,
2643 info = &dbg_port_dspt_cdt_rx_p0_0;
2644 rtw89_write16_mask(rtwdev, info->sel_addr,
2646 rtw89_write16_mask(rtwdev, info->sel_addr,
2652 info = &dbg_port_dspt_cdt_rx_p0_1;
2653 rtw89_write16_mask(rtwdev, info->sel_addr,
2655 rtw89_write16_mask(rtwdev, info->sel_addr,
2660 info = &dbg_port_dspt_cdt_rx_p0_2;
2661 rtw89_write16_mask(rtwdev, info->sel_addr,
2663 rtw89_write16_mask(rtwdev, info->sel_addr,
2668 info = &dbg_port_dspt_cdt_rx_p1;
2669 rtw89_write8_mask(rtwdev, info->sel_addr,
2674 info = &dbg_port_dspt_stf_ctrl;
2675 rtw89_write8_mask(rtwdev, info->sel_addr,
2680 info = &dbg_port_dspt_addr_ctrl;
2681 rtw89_write8_mask(rtwdev, info->sel_addr,
2686 info = &dbg_port_dspt_wde_intf;
2687 rtw89_write8_mask(rtwdev, info->sel_addr,
2692 info = &dbg_port_dspt_ple_intf;
2693 rtw89_write8_mask(rtwdev, info->sel_addr,
2698 info = &dbg_port_dspt_flow_ctrl;
2699 rtw89_write8_mask(rtwdev, info->sel_addr,
2704 info = &dbg_port_pcie_txdma;
2712 info = &dbg_port_pcie_rxdma;
2720 info = &dbg_port_pcie_cvt;
2728 info = &dbg_port_pcie_cxpl;
2736 info = &dbg_port_pcie_io;
2744 info = &dbg_port_pcie_misc;
2752 info = &dbg_port_pcie_misc2;
2764 return info;
2800 const struct rtw89_mac_dbg_port_info *info;
2806 info = rtw89_debug_mac_dbg_port_sel(m, rtwdev, sel);
2807 if (!info) {
2910 seq_printf(m, "Sel addr = 0x%X\n", info->sel_addr);
2911 seq_printf(m, "Read addr = 0x%X\n", info->rd_addr);
2913 for (i = info->srt; i <= info->end; i++) {
2914 switch (info->sel_byte) {
2917 rtw89_write8_mask(rtwdev, info->sel_addr,
2918 info->sel_msk, i);
2922 rtw89_write16_mask(rtwdev, info->sel_addr,
2923 info->sel_msk, i);
2927 rtw89_write32_mask(rtwdev, info->sel_addr,
2928 info->sel_msk, i);
2935 switch (info->rd_byte) {
2939 info->rd_addr, info->rd_msk);
2944 info->rd_addr, info->rd_msk);
2949 info->rd_addr, info->rd_msk);
3367 const struct rtw89_rx_rate_cnt_info *info;
3382 info = &rtw89_rx_rate_cnt_infos[i];
3383 first_rate = info->first_rate[chip->chip_gen];
3387 seq_printf(m, "%10s [", info->rate_mode);
3389 first_rate, info->len);
3390 if (info->ext) {
3393 first_rate + info->len, info->ext);
3428 struct rtw89_pktofld_info *info;
3443 list_for_each_entry(info, pkt_list, list)
3444 seq_printf(m, "%d ", info->id);