Lines Matching defs:pcysta
999 union rtw89_btc_fbtc_cysta_info *pcysta = NULL;
1070 pcysta = &pfwinfo->rpt_fbtc_cysta.finfo;
1073 pcysta->v2 = pfwinfo->rpt_fbtc_cysta.finfo.v2;
1077 pcysta->v3 = pfwinfo->rpt_fbtc_cysta.finfo.v3;
1081 pcysta->v4 = pfwinfo->rpt_fbtc_cysta.finfo.v4;
1085 pcysta->v5 = pfwinfo->rpt_fbtc_cysta.finfo.v5;
1347 if (le16_to_cpu(pcysta->v2.cycles) < BTC_CYSTA_CHK_PERIOD)
1350 if (le32_to_cpu(pcysta->v2.slot_cnt[CXST_LK]) != 0 &&
1351 le32_to_cpu(pcysta->v2.leakrx_cnt) != 0 && dm->tdma_now.rxflctrl) {
1352 if (le32_to_cpu(pcysta->v2.slot_cnt[CXST_LK]) <
1353 BTC_LEAK_AP_TH * le32_to_cpu(pcysta->v2.leakrx_cnt))
1364 if (le16_to_cpu(pcysta->v2.tavg_cycle[CXT_WL]) > wl_slot_set) {
1365 diff_t = le16_to_cpu(pcysta->v2.tavg_cycle[CXT_WL]) - wl_slot_set;
1371 le32_to_cpu(pcysta->v2.slot_cnt[CXST_W1]));
1373 le32_to_cpu(pcysta->v2.slot_cnt[CXST_B1]));
1375 le16_to_cpu(pcysta->v2.cycles));
1377 if (le16_to_cpu(pcysta->v3.cycles) < BTC_CYSTA_CHK_PERIOD)
1380 cnt_leak_slot = le32_to_cpu(pcysta->v3.slot_cnt[CXST_LK]);
1381 cnt_rx_imr = le32_to_cpu(pcysta->v3.leak_slot.cnt_rximr);
1393 wl_slot_real = le16_to_cpu(pcysta->v3.cycle_time.tavg[CXT_WL]);
1404 bt_slot_real = le16_to_cpu(pcysta->v3.cycle_time.tavg[CXT_BT]);
1412 le32_to_cpu(pcysta->v3.slot_cnt[CXST_W1]));
1414 le32_to_cpu(pcysta->v3.slot_cnt[CXST_B1]));
1416 le16_to_cpu(pcysta->v3.cycles));
1418 if (le16_to_cpu(pcysta->v4.cycles) < BTC_CYSTA_CHK_PERIOD)
1421 cnt_leak_slot = le16_to_cpu(pcysta->v4.slot_cnt[CXST_LK]);
1422 cnt_rx_imr = le32_to_cpu(pcysta->v4.leak_slot.cnt_rximr);
1434 wl_slot_real = le16_to_cpu(pcysta->v4.cycle_time.tavg[CXT_WL]);
1445 bt_slot_real = le16_to_cpu(pcysta->v4.cycle_time.tavg[CXT_BT]);
1454 le16_to_cpu(pcysta->v4.slot_cnt[CXST_W1]));
1456 le16_to_cpu(pcysta->v4.slot_cnt[CXST_B1]));
1458 le16_to_cpu(pcysta->v4.cycles));
1462 cnt_leak_slot = le16_to_cpu(pcysta->v5.slot_cnt[CXST_LK]);
1463 cnt_rx_imr = le32_to_cpu(pcysta->v5.leak_slot.cnt_rximr);
1468 if (le16_to_cpu(pcysta->v5.cycles) >= BTC_CYSTA_CHK_PERIOD &&
1476 wl_slot_real = le16_to_cpu(pcysta->v5.cycle_time.tavg[CXT_WL]);
1487 bt_slot_real = le16_to_cpu(pcysta->v5.cycle_time.tavg[CXT_BT]);
1500 le16_to_cpu(pcysta->v5.slot_cnt[CXST_E2G]));
1502 le16_to_cpu(pcysta->v5.slot_cnt[CXST_W1]));
1504 le16_to_cpu(pcysta->v5.slot_cnt[CXST_B1]));
1506 le16_to_cpu(pcysta->v5.cycles));
6826 union rtw89_btc_fbtc_cysta_info *pcysta;
6829 pcysta = &pfwinfo->rpt_fbtc_cysta.finfo;
6831 pcysta->v2 = pfwinfo->rpt_fbtc_cysta.finfo.v2;
6832 except_cnt = le32_to_cpu(pcysta->v2.except_cnt);
6833 exception_map = le32_to_cpu(pcysta->v2.exception);
6835 pcysta->v3 = pfwinfo->rpt_fbtc_cysta.finfo.v3;
6836 except_cnt = le32_to_cpu(pcysta->v3.except_cnt);
6837 exception_map = le32_to_cpu(pcysta->v3.except_map);
6839 pcysta->v4 = pfwinfo->rpt_fbtc_cysta.finfo.v4;
6840 except_cnt = pcysta->v4.except_cnt;
6841 exception_map = le32_to_cpu(pcysta->v4.except_map);
6843 pcysta->v5 = pfwinfo->rpt_fbtc_cysta.finfo.v5;
6844 except_cnt = pcysta->v5.except_cnt;
6845 exception_map = le32_to_cpu(pcysta->v5.except_map);
7079 struct rtw89_btc_fbtc_cysta_v3 *pcysta;
7088 pcysta = &pfwinfo->rpt_fbtc_cysta.finfo.v3;
7092 le16_to_cpu(pcysta->cycles),
7093 le32_to_cpu(pcysta->bcn_cnt[CXBCN_ALL]),
7094 le32_to_cpu(pcysta->bcn_cnt[CXBCN_ALL_OK]),
7095 le32_to_cpu(pcysta->bcn_cnt[CXBCN_BT_SLOT]),
7096 le32_to_cpu(pcysta->bcn_cnt[CXBCN_BT_OK]));
7099 if (!le32_to_cpu(pcysta->slot_cnt[i]))
7103 le32_to_cpu(pcysta->slot_cnt[i]));
7107 seq_printf(m, ", leak_rx:%d", le32_to_cpu(pcysta->leak_slot.cnt_rximr));
7109 if (le32_to_cpu(pcysta->collision_cnt))
7110 seq_printf(m, ", collision:%d", le32_to_cpu(pcysta->collision_cnt));
7112 if (le32_to_cpu(pcysta->skip_cnt))
7113 seq_printf(m, ", skip:%d", le32_to_cpu(pcysta->skip_cnt));
7119 le16_to_cpu(pcysta->cycle_time.tavg[CXT_WL]),
7120 le16_to_cpu(pcysta->cycle_time.tavg[CXT_BT]),
7121 le16_to_cpu(pcysta->leak_slot.tavg) / 1000,
7122 le16_to_cpu(pcysta->leak_slot.tavg) % 1000);
7125 le16_to_cpu(pcysta->cycle_time.tmax[CXT_WL]),
7126 le16_to_cpu(pcysta->cycle_time.tmax[CXT_BT]),
7127 le16_to_cpu(pcysta->leak_slot.tmax) / 1000,
7128 le16_to_cpu(pcysta->leak_slot.tmax) % 1000);
7131 le16_to_cpu(pcysta->cycle_time.tmaxdiff[CXT_WL]),
7132 le16_to_cpu(pcysta->cycle_time.tmaxdiff[CXT_BT]));
7134 cycle = le16_to_cpu(pcysta->cycles);
7161 le16_to_cpu(pcysta->slot_step_time[store_index]));
7163 a2dp_trx = &pcysta->a2dp_trx[store_index];
7173 le16_to_cpu(pcysta->slot_step_time[store_index + 1]));
7175 a2dp_trx = &pcysta->a2dp_trx[store_index + 1];
7191 le16_to_cpu(pcysta->a2dp_ept.cnt),
7192 le16_to_cpu(pcysta->a2dp_ept.cnt_timeout));
7195 le16_to_cpu(pcysta->a2dp_ept.tavg),
7196 le16_to_cpu(pcysta->a2dp_ept.tmax));
7209 struct rtw89_btc_fbtc_cysta_v4 *pcysta;
7218 pcysta = &pfwinfo->rpt_fbtc_cysta.finfo.v4;
7222 le16_to_cpu(pcysta->cycles),
7223 le16_to_cpu(pcysta->bcn_cnt[CXBCN_ALL]),
7224 le16_to_cpu(pcysta->bcn_cnt[CXBCN_ALL_OK]),
7225 le16_to_cpu(pcysta->bcn_cnt[CXBCN_BT_SLOT]),
7226 le16_to_cpu(pcysta->bcn_cnt[CXBCN_BT_OK]));
7229 if (!le16_to_cpu(pcysta->slot_cnt[i]))
7233 le16_to_cpu(pcysta->slot_cnt[i]));
7238 le32_to_cpu(pcysta->leak_slot.cnt_rximr));
7240 if (pcysta->collision_cnt)
7241 seq_printf(m, ", collision:%d", pcysta->collision_cnt);
7243 if (le16_to_cpu(pcysta->skip_cnt))
7245 le16_to_cpu(pcysta->skip_cnt));
7251 le16_to_cpu(pcysta->cycle_time.tavg[CXT_WL]),
7252 le16_to_cpu(pcysta->cycle_time.tavg[CXT_BT]),
7253 le16_to_cpu(pcysta->leak_slot.tavg) / 1000,
7254 le16_to_cpu(pcysta->leak_slot.tavg) % 1000);
7257 le16_to_cpu(pcysta->cycle_time.tmax[CXT_WL]),
7258 le16_to_cpu(pcysta->cycle_time.tmax[CXT_BT]),
7259 le16_to_cpu(pcysta->leak_slot.tmax) / 1000,
7260 le16_to_cpu(pcysta->leak_slot.tmax) % 1000);
7263 le16_to_cpu(pcysta->cycle_time.tmaxdiff[CXT_WL]),
7264 le16_to_cpu(pcysta->cycle_time.tmaxdiff[CXT_BT]));
7266 cycle = le16_to_cpu(pcysta->cycles);
7293 le16_to_cpu(pcysta->slot_step_time[store_index]));
7295 a2dp_trx = &pcysta->a2dp_trx[store_index];
7305 le16_to_cpu(pcysta->slot_step_time[store_index + 1]));
7307 a2dp_trx = &pcysta->a2dp_trx[store_index + 1];
7323 le16_to_cpu(pcysta->a2dp_ept.cnt),
7324 le16_to_cpu(pcysta->a2dp_ept.cnt_timeout));
7327 le16_to_cpu(pcysta->a2dp_ept.tavg),
7328 le16_to_cpu(pcysta->a2dp_ept.tmax));
7341 struct rtw89_btc_fbtc_cysta_v5 *pcysta;
7350 pcysta = &pfwinfo->rpt_fbtc_cysta.finfo.v5;
7354 le16_to_cpu(pcysta->cycles),
7355 le16_to_cpu(pcysta->bcn_cnt[CXBCN_ALL]),
7356 le16_to_cpu(pcysta->bcn_cnt[CXBCN_ALL_OK]),
7357 le16_to_cpu(pcysta->bcn_cnt[CXBCN_BT_SLOT]),
7358 le16_to_cpu(pcysta->bcn_cnt[CXBCN_BT_OK]));
7361 if (!le16_to_cpu(pcysta->slot_cnt[i]))
7365 le16_to_cpu(pcysta->slot_cnt[i]));
7370 le32_to_cpu(pcysta->leak_slot.cnt_rximr));
7372 if (pcysta->collision_cnt)
7373 seq_printf(m, ", collision:%d", pcysta->collision_cnt);
7375 if (le16_to_cpu(pcysta->skip_cnt))
7377 le16_to_cpu(pcysta->skip_cnt));
7383 le16_to_cpu(pcysta->cycle_time.tavg[CXT_WL]),
7384 le16_to_cpu(pcysta->cycle_time.tavg[CXT_BT]),
7385 le16_to_cpu(pcysta->leak_slot.tavg) / 1000,
7386 le16_to_cpu(pcysta->leak_slot.tavg) % 1000);
7389 le16_to_cpu(pcysta->cycle_time.tmax[CXT_WL]),
7390 le16_to_cpu(pcysta->cycle_time.tmax[CXT_BT]),
7391 le16_to_cpu(pcysta->leak_slot.tmax) / 1000,
7392 le16_to_cpu(pcysta->leak_slot.tmax) % 1000);
7394 cycle = le16_to_cpu(pcysta->cycles);
7424 le16_to_cpu(pcysta->slot_step_time[store_index]));
7426 a2dp_trx = &pcysta->a2dp_trx[store_index];
7436 le16_to_cpu(pcysta->slot_step_time[store_index + 1]));
7438 a2dp_trx = &pcysta->a2dp_trx[store_index + 1];
7454 le16_to_cpu(pcysta->a2dp_ept.cnt),
7455 le16_to_cpu(pcysta->a2dp_ept.cnt_timeout));
7458 le16_to_cpu(pcysta->a2dp_ept.tavg),
7459 le16_to_cpu(pcysta->a2dp_ept.tmax));