Lines Matching refs:rtwdev
23 static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path,
44 static int rtw8822c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
46 struct rtw_efuse *efuse = &rtwdev->efuse;
69 switch (rtw_hci_type(rtwdev)) {
87 static void rtw8822c_header_file_init(struct rtw_dev *rtwdev, bool pre)
89 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN);
90 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_PI_ON);
91 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN);
92 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_PI_ON);
95 rtw_write32_clr(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN);
97 rtw_write32_set(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN);
100 static void rtw8822c_bb_reset(struct rtw_dev *rtwdev)
102 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_BB_RSTB);
103 rtw_write16_clr(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_BB_RSTB);
104 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_BB_RSTB);
107 static void rtw8822c_dac_backup_reg(struct rtw_dev *rtwdev,
123 backup[i].val = rtw_read32(rtwdev, addrs[i]);
129 val = rtw_read_rf(rtwdev, path, reg, RFREG_MASK);
136 static void rtw8822c_dac_restore_reg(struct rtw_dev *rtwdev,
144 rtw_restore_reg(rtwdev, backup, DACK_REG_8822C);
150 rtw_write_rf(rtwdev, path, reg, RFREG_MASK, val);
155 static void rtw8822c_rf_minmax_cmp(struct rtw_dev *rtwdev, u32 value,
184 static void __rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *v1, u32 *v2)
197 static void rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *iv, u32 *qv)
203 __rtw8822c_dac_iq_sort(rtwdev, &iv[j], &iv[j + 1]);
204 __rtw8822c_dac_iq_sort(rtwdev, &qv[j], &qv[j + 1]);
209 static void rtw8822c_dac_iq_offset(struct rtw_dev *rtwdev, u32 *vec, u32 *val)
273 static bool rtw8822c_dac_iq_check(struct rtw_dev *rtwdev, u32 value)
280 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] Error overflow\n");
286 static void rtw8822c_dac_cal_iq_sample(struct rtw_dev *rtwdev, u32 *iv, u32 *qv)
293 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
297 if (rtw8822c_dac_iq_check(rtwdev, iv[i]) &&
298 rtw8822c_dac_iq_check(rtwdev, qv[i]))
303 static void rtw8822c_dac_cal_iq_search(struct rtw_dev *rtwdev,
318 rtw8822c_rf_minmax_cmp(rtwdev, iv[i], &i_min, &i_max);
319 rtw8822c_rf_minmax_cmp(rtwdev, qv[i], &q_min, &q_max);
336 rtw_dbg(rtwdev, RTW_DBG_RFK,
339 rtw_dbg(rtwdev, RTW_DBG_RFK,
343 rtw8822c_dac_iq_sort(rtwdev, iv, qv);
346 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
349 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
357 rtw8822c_dac_iq_offset(rtwdev, iv, i_value);
358 rtw8822c_dac_iq_offset(rtwdev, qv, q_value);
361 static void rtw8822c_dac_cal_rf_mode(struct rtw_dev *rtwdev,
367 rf_a = rtw_read_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK);
368 rf_b = rtw_read_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK);
370 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-A=0x%05x\n", rf_a);
371 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-B=0x%05x\n", rf_b);
373 rtw8822c_dac_cal_iq_sample(rtwdev, iv, qv);
374 rtw8822c_dac_cal_iq_search(rtwdev, iv, qv, i_value, q_value);
377 static void rtw8822c_dac_bb_setting(struct rtw_dev *rtwdev)
379 rtw_write32_mask(rtwdev, 0x1d58, 0xff8, 0x1ff);
380 rtw_write32_mask(rtwdev, 0x1a00, 0x3, 0x2);
381 rtw_write32_mask(rtwdev, 0x1a14, 0x300, 0x3);
382 rtw_write32(rtwdev, 0x1d70, 0x7e7e7e7e);
383 rtw_write32_mask(rtwdev, 0x180c, 0x3, 0x0);
384 rtw_write32_mask(rtwdev, 0x410c, 0x3, 0x0);
385 rtw_write32(rtwdev, 0x1b00, 0x00000008);
386 rtw_write8(rtwdev, 0x1bcc, 0x3f);
387 rtw_write32(rtwdev, 0x1b00, 0x0000000a);
388 rtw_write8(rtwdev, 0x1bcc, 0x3f);
389 rtw_write32_mask(rtwdev, 0x1e24, BIT(31), 0x0);
390 rtw_write32_mask(rtwdev, 0x1e28, 0xf, 0x3);
393 static void rtw8822c_dac_cal_adc(struct rtw_dev *rtwdev,
396 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
402 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK path(%d)\n", path);
418 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x0);
420 rtw_write32(rtwdev, base_addr + 0x30, 0x30db8041);
421 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0);
422 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
423 rtw_write32(rtwdev, base_addr + 0x10, 0x02dd08c4);
424 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260);
425 rtw_write_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK, 0x10000);
426 rtw_write_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK, 0x10000);
428 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK count=%d\n", i);
429 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8003);
430 rtw_write32(rtwdev, 0x1c24, 0x00010002);
431 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc);
432 rtw_dbg(rtwdev, RTW_DBG_RFK,
445 rtw_write32(rtwdev, base_addr + 0x68, temp);
447 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK 0x%08x=0x08%x\n",
450 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8103);
451 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc);
452 rtw_dbg(rtwdev, RTW_DBG_RFK,
463 rtw_write32(rtwdev, 0x1c3c, 0x00000003);
464 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260);
465 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4);
468 rtw_write_rf(rtwdev, path, 0x8f, BIT(13), 0x1);
471 static void rtw8822c_dac_cal_step1(struct rtw_dev *rtwdev, u8 path)
473 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
480 rtw_write32(rtwdev, base_addr + 0x68, dm_info->dack_adck[path]);
481 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
483 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0);
484 rtw_write32(rtwdev, 0x1c38, 0xffffffff);
486 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
487 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
488 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88);
489 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff81);
490 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208);
491 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88);
492 rtw_write32(rtwdev, base_addr + 0xd8, 0x0008ff81);
493 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208);
494 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000);
496 rtw_write32(rtwdev, base_addr + 0xbc, 0x000aff8d);
498 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89);
499 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89);
501 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000);
502 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000);
504 if (!check_hw_ready(rtwdev, read_addr + 0x08, 0x7fff80, 0xffff) ||
505 !check_hw_ready(rtwdev, read_addr + 0x34, 0x7fff80, 0xffff))
506 rtw_err(rtwdev, "failed to wait for dack ready\n");
507 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000);
509 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87);
510 rtw_write32(rtwdev, 0x9b4, 0xdb6db600);
511 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
512 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87);
513 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000);
516 static void rtw8822c_dac_cal_step2(struct rtw_dev *rtwdev,
523 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, 0x0);
524 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, 0x8);
525 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, 0x0);
526 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, 0x8);
528 rtw_write32(rtwdev, 0x1b00, 0x00000008);
529 rtw_write8(rtwdev, 0x1bcc, 0x03f);
530 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
531 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
532 rtw_write32(rtwdev, 0x1c3c, 0x00088103);
534 rtw8822c_dac_cal_rf_mode(rtwdev, &ic_in, &qc_in);
561 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] before i=0x%x, q=0x%x\n", ic_in, qc_in);
562 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] after i=0x%x, q=0x%x\n", ic, qc);
565 static void rtw8822c_dac_cal_step3(struct rtw_dev *rtwdev, u8 path,
580 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
581 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
582 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
583 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88);
584 rtw_write32(rtwdev, base_addr + 0xbc, 0xc008ff81);
585 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208);
586 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, ic & 0xf);
587 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, (ic & 0xf0) >> 4);
588 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88);
589 rtw_write32(rtwdev, base_addr + 0xd8, 0xe008ff81);
590 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208);
591 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, qc & 0xf);
592 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, (qc & 0xf0) >> 4);
593 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000);
595 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x6);
597 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89);
598 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89);
600 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000);
601 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000);
603 if (!check_hw_ready(rtwdev, read_addr + 0x24, 0x07f80000, ic) ||
604 !check_hw_ready(rtwdev, read_addr + 0x50, 0x07f80000, qc))
605 rtw_err(rtwdev, "failed to write IQ vector to hardware\n");
606 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000);
608 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x3);
609 rtw_write32(rtwdev, 0x9b4, 0xdb6db600);
613 rtw_write32(rtwdev, base_addr + 0x68, temp);
614 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
615 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000);
616 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc);
638 rtw_dbg(rtwdev, RTW_DBG_RFK,
642 static void rtw8822c_dac_cal_step4(struct rtw_dev *rtwdev, u8 path)
646 rtw_write32(rtwdev, base_addr + 0x68, 0x0);
647 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4);
648 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0x1, 0x0);
649 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x1);
652 static void rtw8822c_dac_cal_backup_vec(struct rtw_dev *rtwdev,
655 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
663 rtw_write32_mask(rtwdev, w_addr, 0xf0000000, i);
664 val = (u16)rtw_read32_mask(rtwdev, r_addr, 0x7fc0000);
669 static void rtw8822c_dac_cal_backup_path(struct rtw_dev *rtwdev, u8 path)
681 rtw8822c_dac_cal_backup_vec(rtwdev, path, 0, w_addr, r_addr);
686 rtw8822c_dac_cal_backup_vec(rtwdev, path, 1, w_addr, r_addr);
689 static void rtw8822c_dac_cal_backup_dck(struct rtw_dev *rtwdev)
691 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
694 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000);
696 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_1, 0xf);
698 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000);
700 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_1, 0xf);
703 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000);
705 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_1, 0xf);
707 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000);
709 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_1, 0xf);
713 static void rtw8822c_dac_cal_backup(struct rtw_dev *rtwdev)
717 temp[0] = rtw_read32(rtwdev, 0x1860);
718 temp[1] = rtw_read32(rtwdev, 0x4160);
719 temp[2] = rtw_read32(rtwdev, 0x9b4);
722 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
725 rtw_write32_clr(rtwdev, 0x1830, BIT(30));
726 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c);
727 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_A);
730 rtw_write32_clr(rtwdev, 0x4130, BIT(30));
731 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c);
732 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_B);
734 rtw8822c_dac_cal_backup_dck(rtwdev);
735 rtw_write32_set(rtwdev, 0x1830, BIT(30));
736 rtw_write32_set(rtwdev, 0x4130, BIT(30));
738 rtw_write32(rtwdev, 0x1860, temp[0]);
739 rtw_write32(rtwdev, 0x4160, temp[1]);
740 rtw_write32(rtwdev, 0x9b4, temp[2]);
743 static void rtw8822c_dac_cal_restore_dck(struct rtw_dev *rtwdev)
745 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
748 rtw_write32_set(rtwdev, REG_DCKA_I_0, BIT(19));
750 rtw_write32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000, val);
752 rtw_write32_mask(rtwdev, REG_DCKA_I_1, 0xf, val);
754 rtw_write32_set(rtwdev, REG_DCKA_Q_0, BIT(19));
756 rtw_write32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000, val);
758 rtw_write32_mask(rtwdev, REG_DCKA_Q_1, 0xf, val);
760 rtw_write32_set(rtwdev, REG_DCKB_I_0, BIT(19));
762 rtw_write32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000, val);
764 rtw_write32_mask(rtwdev, REG_DCKB_I_1, 0xf, val);
766 rtw_write32_set(rtwdev, REG_DCKB_Q_0, BIT(19));
768 rtw_write32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000, val);
770 rtw_write32_mask(rtwdev, REG_DCKB_Q_1, 0xf, val);
773 static void rtw8822c_dac_cal_restore_prepare(struct rtw_dev *rtwdev)
775 rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
777 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x0);
778 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x0);
779 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x0);
780 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x0);
782 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x0);
783 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c);
784 rtw_write32_mask(rtwdev, 0x18b4, BIT(0), 0x1);
785 rtw_write32_mask(rtwdev, 0x18d0, BIT(0), 0x1);
787 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x0);
788 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c);
789 rtw_write32_mask(rtwdev, 0x41b4, BIT(0), 0x1);
790 rtw_write32_mask(rtwdev, 0x41d0, BIT(0), 0x1);
792 rtw_write32_mask(rtwdev, 0x18b0, 0xf00, 0x0);
793 rtw_write32_mask(rtwdev, 0x18c0, BIT(14), 0x0);
794 rtw_write32_mask(rtwdev, 0x18cc, 0xf00, 0x0);
795 rtw_write32_mask(rtwdev, 0x18dc, BIT(14), 0x0);
797 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x0);
798 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x0);
799 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x1);
800 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x1);
802 rtw8822c_dac_cal_restore_dck(rtwdev);
804 rtw_write32_mask(rtwdev, 0x18c0, 0x38000, 0x7);
805 rtw_write32_mask(rtwdev, 0x18dc, 0x38000, 0x7);
806 rtw_write32_mask(rtwdev, 0x41c0, 0x38000, 0x7);
807 rtw_write32_mask(rtwdev, 0x41dc, 0x38000, 0x7);
809 rtw_write32_mask(rtwdev, 0x18b8, BIT(26) | BIT(25), 0x1);
810 rtw_write32_mask(rtwdev, 0x18d4, BIT(26) | BIT(25), 0x1);
812 rtw_write32_mask(rtwdev, 0x41b0, 0xf00, 0x0);
813 rtw_write32_mask(rtwdev, 0x41c0, BIT(14), 0x0);
814 rtw_write32_mask(rtwdev, 0x41cc, 0xf00, 0x0);
815 rtw_write32_mask(rtwdev, 0x41dc, BIT(14), 0x0);
817 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x0);
818 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x0);
819 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x1);
820 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x1);
822 rtw_write32_mask(rtwdev, 0x41b8, BIT(26) | BIT(25), 0x1);
823 rtw_write32_mask(rtwdev, 0x41d4, BIT(26) | BIT(25), 0x1);
826 static bool rtw8822c_dac_cal_restore_wait(struct rtw_dev *rtwdev,
832 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x0);
833 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x2);
835 if (rtw_read32_mask(rtwdev, target_addr, 0xf) == 0x6)
843 static bool rtw8822c_dac_cal_restore_path(struct rtw_dev *rtwdev, u8 path)
845 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
857 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_i, w_i + 0x8))
861 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0);
863 rtw_write32_mask(rtwdev, w_i + 0x4, 0xff8, value);
864 rtw_write32_mask(rtwdev, w_i, 0xf0000000, i);
865 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x1);
868 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0);
870 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_q, w_q + 0x8))
874 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0);
876 rtw_write32_mask(rtwdev, w_q + 0x4, 0xff8, value);
877 rtw_write32_mask(rtwdev, w_q, 0xf0000000, i);
878 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x1);
880 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0);
882 rtw_write32_mask(rtwdev, w_i + 0x8, BIT(26) | BIT(25), 0x0);
883 rtw_write32_mask(rtwdev, w_q + 0x8, BIT(26) | BIT(25), 0x0);
884 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(0), 0x0);
885 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(0), 0x0);
890 static bool __rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev)
892 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_A))
895 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_B))
901 static bool rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev)
903 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
913 temp[0] = rtw_read32(rtwdev, 0x1860);
914 temp[1] = rtw_read32(rtwdev, 0x4160);
915 temp[2] = rtw_read32(rtwdev, 0x9b4);
917 rtw8822c_dac_cal_restore_prepare(rtwdev);
918 if (!check_hw_ready(rtwdev, 0x2808, 0x7fff80, 0xffff) ||
919 !check_hw_ready(rtwdev, 0x2834, 0x7fff80, 0xffff) ||
920 !check_hw_ready(rtwdev, 0x4508, 0x7fff80, 0xffff) ||
921 !check_hw_ready(rtwdev, 0x4534, 0x7fff80, 0xffff))
924 if (!__rtw8822c_dac_cal_restore(rtwdev)) {
925 rtw_err(rtwdev, "failed to restore dack vectors\n");
929 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x1);
930 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1);
931 rtw_write32(rtwdev, 0x1860, temp[0]);
932 rtw_write32(rtwdev, 0x4160, temp[1]);
933 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x1);
934 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x1);
935 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x1);
936 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x1);
937 rtw_write32(rtwdev, 0x9b4, temp[2]);
942 static void rtw8822c_rf_dac_cal(struct rtw_dev *rtwdev)
951 if (rtw8822c_dac_cal_restore(rtwdev))
956 rtw8822c_dac_backup_reg(rtwdev, backup, backup_rf);
958 rtw8822c_dac_bb_setting(rtwdev);
961 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_A, &adc_ic_a, &adc_qc_a);
963 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_A);
964 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_A, &ic, &qc);
968 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_A, adc_ic_a, adc_qc_a,
974 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_A);
977 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_B, &adc_ic_b, &adc_qc_b);
979 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_B);
980 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_B, &ic, &qc);
984 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_B, adc_ic_b, adc_qc_b,
990 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_B);
992 rtw_write32(rtwdev, 0x1b00, 0x00000008);
993 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1);
994 rtw_write8(rtwdev, 0x1bcc, 0x0);
995 rtw_write32(rtwdev, 0x1b00, 0x0000000a);
996 rtw_write8(rtwdev, 0x1bcc, 0x0);
998 rtw8822c_dac_restore_reg(rtwdev, backup, backup_rf);
1001 rtw8822c_dac_cal_backup(rtwdev);
1003 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: ic=0x%x, qc=0x%x\n", ic_a, qc_a);
1004 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: ic=0x%x, qc=0x%x\n", ic_b, qc_b);
1005 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: i=0x%x, q=0x%x\n", i_a, q_a);
1006 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: i=0x%x, q=0x%x\n", i_b, q_b);
1009 static void rtw8822c_rf_x2_check(struct rtw_dev *rtwdev)
1014 x2k_busy = rtw_read_rf(rtwdev, RF_PATH_A, 0xb8, BIT(15));
1016 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0xC4440);
1017 rtw_write_rf(rtwdev, RF_PATH_A, 0xba, RFREG_MASK, 0x6840D);
1018 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0x80440);
1023 static void rtw8822c_set_power_trim(struct rtw_dev *rtwdev, s8 bb_gain[2][8])
1027 rtw_write_rf(rtwdev, _path, 0x33, RFREG_MASK, _seq); \
1028 rtw_write_rf(rtwdev, _path, 0x3f, RFREG_MASK, \
1033 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1034 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 1);
1050 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 0);
1055 static void rtw8822c_power_trim(struct rtw_dev *rtwdev)
1067 rtw_read8_physical_efuse(rtwdev, rf_efuse_2g[i], &pg_pwr);
1076 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1077 rtw_read8_physical_efuse(rtwdev, rf_efuse_5g[path][i],
1087 rtw8822c_set_power_trim(rtwdev, bb_gain);
1089 rtw_write32_mask(rtwdev, REG_DIS_DPD, DIS_DPD_MASK, DIS_DPD_RATEALL);
1092 static void rtw8822c_thermal_trim(struct rtw_dev *rtwdev)
1097 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1098 rtw_read8_physical_efuse(rtwdev, rf_efuse[path], &pg_therm);
1106 rtw_write_rf(rtwdev, path, 0x43, RF_THEMAL_MASK, thermal[path]);
1110 static void rtw8822c_pa_bias(struct rtw_dev *rtwdev)
1116 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1117 rtw_read8_physical_efuse(rtwdev, rf_efuse_2g[path],
1122 rtw_write_rf(rtwdev, path, RF_PA, RF_PABIAS_2G_MASK, pg_pa_bias);
1124 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1125 rtw_read8_physical_efuse(rtwdev, rf_efuse_5g[path],
1128 rtw_write_rf(rtwdev, path, RF_PA, RF_PABIAS_5G_MASK, pg_pa_bias);
1132 static void rtw8822c_rfk_handshake(struct rtw_dev *rtwdev, bool is_before_k)
1134 struct rtw_dm_info *dm = &rtwdev->dm_info;
1140 rtw_dbg(rtwdev, RTW_DBG_RFK,
1146 rtwdev, REG_PMC_DBG_CTRL1,
1149 rtw_dbg(rtwdev, RTW_DBG_RFK,
1155 rtw_fw_inform_rfk_status(rtwdev, true);
1159 rtwdev, REG_ARFR4, BIT_WL_RFK);
1161 rtw_dbg(rtwdev, RTW_DBG_RFK,
1164 rtw_fw_inform_rfk_status(rtwdev, false);
1167 rtwdev, REG_ARFR4,
1170 rtw_dbg(rtwdev, RTW_DBG_RFK,
1173 rtw_dbg(rtwdev, RTW_DBG_RFK,
1178 static void rtw8822c_rfk_power_save(struct rtw_dev *rtwdev,
1183 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1184 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path);
1185 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_PS_EN,
1190 static void rtw8822c_txgapk_backup_bb_reg(struct rtw_dev *rtwdev, const u32 reg[],
1196 reg_backup[i] = rtw_read32(rtwdev, reg[i]);
1198 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] Backup BB 0x%x = 0x%x\n",
1203 static void rtw8822c_txgapk_reload_bb_reg(struct rtw_dev *rtwdev,
1210 rtw_write32(rtwdev, reg[i], reg_backup[i]);
1211 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] Reload BB 0x%x = 0x%x\n",
1216 static bool check_rf_status(struct rtw_dev *rtwdev, u8 status)
1220 reg_rf0_a = (u8)rtw_read_rf(rtwdev, RF_PATH_A,
1222 reg_rf0_b = (u8)rtw_read_rf(rtwdev, RF_PATH_B,
1231 static void rtw8822c_txgapk_tx_pause(struct rtw_dev *rtwdev)
1236 rtw_write8(rtwdev, REG_TXPAUSE, BIT_AC_QUEUE);
1237 rtw_write32_mask(rtwdev, REG_TX_FIFO, BIT_STOP_TX, 0x2);
1240 2, 5000, false, rtwdev, 2);
1242 rtw_warn(rtwdev, "failed to pause TX\n");
1244 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] Tx pause!!\n");
1247 static void rtw8822c_txgapk_bb_dpk(struct rtw_dev *rtwdev, u8 path)
1249 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__);
1251 rtw_write32_mask(rtwdev, REG_ENFN, BIT_IQK_DPK_EN, 0x1);
1252 rtw_write32_mask(rtwdev, REG_CH_DELAY_EXTR2,
1254 rtw_write32_mask(rtwdev, REG_CH_DELAY_EXTR2,
1256 rtw_write32_mask(rtwdev, REG_CH_DELAY_EXTR2, BIT_EN_IOQ_IQK_DPK, 0x1);
1257 rtw_write32_mask(rtwdev, REG_CH_DELAY_EXTR2, BIT_TST_IQK2SET_SRC, 0x0);
1258 rtw_write32_mask(rtwdev, REG_CCA_OFF, BIT_CCA_ON_BY_PW, 0x1ff);
1261 rtw_write32_mask(rtwdev, REG_RFTXEN_GCK_A,
1263 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_DIS_SHARERX_TXGAT, 0x1);
1264 rtw_write32_mask(rtwdev, REG_DIS_SHARE_RX_A,
1266 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_3WIRE_EN, 0x0);
1268 rtw_write32_mask(rtwdev, REG_RFTXEN_GCK_B,
1270 rtw_write32_mask(rtwdev, REG_3WIRE2,
1272 rtw_write32_mask(rtwdev, REG_DIS_SHARE_RX_B,
1274 rtw_write32_mask(rtwdev, REG_3WIRE2, BIT_3WIRE_EN, 0x0);
1276 rtw_write32_mask(rtwdev, REG_CCKSB, BIT_BBMODE, 0x2);
1279 static void rtw8822c_txgapk_afe_dpk(struct rtw_dev *rtwdev, u8 path)
1283 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__);
1290 rtw_err(rtwdev, "[TXGAPK] unknown path %d!!\n", path);
1294 rtw_write32_mask(rtwdev, REG_IQK_CTRL, MASKDWORD, MASKDWORD);
1295 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x700f0001);
1296 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x700f0001);
1297 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x701f0001);
1298 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x702f0001);
1299 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x703f0001);
1300 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x704f0001);
1301 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x705f0001);
1302 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x706f0001);
1303 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x707f0001);
1304 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x708f0001);
1305 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x709f0001);
1306 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70af0001);
1307 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70bf0001);
1308 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70cf0001);
1309 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70df0001);
1310 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ef0001);
1311 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ff0001);
1312 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ff0001);
1315 static void rtw8822c_txgapk_afe_dpk_restore(struct rtw_dev *rtwdev, u8 path)
1319 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__);
1326 rtw_err(rtwdev, "[TXGAPK] unknown path %d!!\n", path);
1329 rtw_write32_mask(rtwdev, REG_IQK_CTRL, MASKDWORD, 0xffa1005e);
1330 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x700b8041);
1331 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70144041);
1332 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70244041);
1333 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70344041);
1334 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70444041);
1335 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x705b8041);
1336 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70644041);
1337 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x707b8041);
1338 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x708b8041);
1339 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x709b8041);
1340 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ab8041);
1341 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70bb8041);
1342 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70cb8041);
1343 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70db8041);
1344 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70eb8041);
1345 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70fb8041);
1348 static void rtw8822c_txgapk_bb_dpk_restore(struct rtw_dev *rtwdev, u8 path)
1350 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__);
1352 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x0);
1353 rtw_write_rf(rtwdev, path, RF_DIS_BYPASS_TXBB, BIT_TIA_BYPASS, 0x0);
1354 rtw_write_rf(rtwdev, path, RF_DIS_BYPASS_TXBB, BIT_TXBB, 0x0);
1356 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, 0x0);
1357 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
1358 rtw_write32_mask(rtwdev, REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0);
1359 rtw_write32_mask(rtwdev, REG_R_CONFIG, MASKBYTE0, 0x00);
1360 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, 0x1);
1361 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
1362 rtw_write32_mask(rtwdev, REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0);
1363 rtw_write32_mask(rtwdev, REG_R_CONFIG, MASKBYTE0, 0x00);
1364 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, 0x0);
1365 rtw_write32_mask(rtwdev, REG_CCA_OFF, BIT_CCA_ON_BY_PW, 0x0);
1368 rtw_write32_mask(rtwdev, REG_RFTXEN_GCK_A,
1370 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_DIS_SHARERX_TXGAT, 0x0);
1371 rtw_write32_mask(rtwdev, REG_DIS_SHARE_RX_A,
1373 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_3WIRE_EN, 0x3);
1375 rtw_write32_mask(rtwdev, REG_RFTXEN_GCK_B,
1377 rtw_write32_mask(rtwdev, REG_3WIRE2,
1379 rtw_write32_mask(rtwdev, REG_DIS_SHARE_RX_B,
1381 rtw_write32_mask(rtwdev, REG_3WIRE2, BIT_3WIRE_EN, 0x3);
1384 rtw_write32_mask(rtwdev, REG_CCKSB, BIT_BBMODE, 0x0);
1385 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_CFIR_EN, 0x5);
1388 static bool _rtw8822c_txgapk_gain_valid(struct rtw_dev *rtwdev, u32 gain)
1397 static void _rtw8822c_txgapk_write_gain_bb_table(struct rtw_dev *rtwdev,
1400 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk;
1404 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path);
1408 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x0);
1411 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x2);
1414 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x3);
1417 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x4);
1423 rtw_write32_mask(rtwdev, REG_TX_GAIN_SET, MASKBYTE0, 0x88);
1428 if (_rtw8822c_txgapk_gain_valid(rtwdev, v)) {
1433 rtw_dbg(rtwdev, RTW_DBG_RFK,
1440 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN, tmp_3f);
1441 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_I_GAIN, gain);
1442 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_GAIN_RST, 0x1);
1443 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_GAIN_RST, 0x0);
1445 rtw_dbg(rtwdev, RTW_DBG_RFK,
1451 static void rtw8822c_txgapk_write_gain_bb_table(struct rtw_dev *rtwdev)
1455 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s channel=%d\n",
1456 __func__, rtwdev->dm_info.gapk.channel);
1459 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1460 _rtw8822c_txgapk_write_gain_bb_table(rtwdev,
1466 static void rtw8822c_txgapk_read_offset(struct rtw_dev *rtwdev, u8 path)
1472 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk;
1481 rtw_warn(rtwdev, "[TXGAPK] wrong path %d\n", path);
1485 rtw_write32_mask(rtwdev, REG_ANTMAP0, BIT_ANT_PATH, path + 1);
1486 rtw_write32_mask(rtwdev, REG_TXLGMAP, MASKDWORD, 0xe4e40000);
1487 rtw_write32_mask(rtwdev, REG_TXANTSEG, BIT_ANTSEG, 0x3);
1488 rtw_write32_mask(rtwdev, path_setting[path], MASK20BITS, 0x33312);
1489 rtw_write32_mask(rtwdev, path_setting[path], BIT_PATH_EN, 0x1);
1490 rtw_write32_mask(rtwdev, set_pi[path], BITS_RFC_DIRECT, 0x0);
1491 rtw_write_rf(rtwdev, path, RF_LUTDBG, BIT_TXA_TANK, 0x1);
1492 rtw_write_rf(rtwdev, path, RF_IDAC, BIT_TX_MODE, 0x820);
1493 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path);
1494 rtw_write32_mask(rtwdev, REG_IQKSTAT, MASKBYTE0, 0x0);
1496 rtw_write32_mask(rtwdev, REG_TX_TONE_IDX, MASKBYTE0, 0x018);
1499 rtw_write32_mask(rtwdev, REG_R_CONFIG, MASKBYTE0, BIT_2G_SWING);
1501 rtw_write32_mask(rtwdev, REG_R_CONFIG, MASKBYTE0, BIT_5G_SWING);
1504 rtw_write32_mask(rtwdev, REG_NCTL0, MASKDWORD, cfg1_1b00[path]);
1505 rtw_write32_mask(rtwdev, REG_NCTL0, MASKDWORD, cfg2_1b00[path]);
1509 rtwdev, REG_RPT_CIP, BIT_RPT_CIP_STATUS);
1511 rtw_write32_mask(rtwdev, set_pi[path], BITS_RFC_DIRECT, 0x2);
1512 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path);
1513 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_EN, 0x1);
1514 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x12);
1515 rtw_write32_mask(rtwdev, REG_TX_GAIN_SET, BIT_GAPK_RPT_IDX, 0x3);
1516 val = rtw_read32(rtwdev, REG_STAT_RPT);
1527 rtw_write32_mask(rtwdev, REG_TX_GAIN_SET, BIT_GAPK_RPT_IDX, 0x4);
1528 val = rtw_read32(rtwdev, REG_STAT_RPT);
1538 rtw_dbg(rtwdev, RTW_DBG_RFK,
1543 static void rtw8822c_txgapk_calculate_offset(struct rtw_dev *rtwdev, u8 path)
1547 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk;
1551 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s channel=%d\n",
1554 rtw8822c_txgapk_backup_bb_reg(rtwdev, bb_reg,
1558 rtw_write32_mask(rtwdev,
1560 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path);
1561 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x3f);
1562 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
1563 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1);
1564 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x5000f);
1565 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_RF_GAIN, 0x0);
1566 rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x1);
1567 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0f);
1568 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1);
1569 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x1);
1570 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0);
1571 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x1);
1573 rtw_write32_mask(rtwdev, REG_IQKSTAT, MASKBYTE0, 0x00);
1574 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x0);
1576 rtw8822c_txgapk_read_offset(rtwdev, path);
1577 rtw_dbg(rtwdev, RTW_DBG_RFK, "=============================\n");
1580 rtw_write32_mask(rtwdev,
1582 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path);
1583 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x3f);
1584 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
1585 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1);
1586 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x50011);
1587 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x3);
1588 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_ATT, 0x3);
1589 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_SW, 0x1);
1590 rtw_write_rf(rtwdev, path,
1592 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0x12);
1593 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1);
1594 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0);
1595 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x1);
1596 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RF_MODE, 0x5);
1598 rtw_write32_mask(rtwdev, REG_IQKSTAT, MASKBYTE0, 0x0);
1601 rtw_write32_mask(rtwdev,
1604 rtw_write32_mask(rtwdev,
1607 rtw_write32_mask(rtwdev,
1610 rtw8822c_txgapk_read_offset(rtwdev, path);
1611 rtw_dbg(rtwdev, RTW_DBG_RFK, "=============================\n");
1613 rtw8822c_txgapk_reload_bb_reg(rtwdev, bb_reg,
1617 static void rtw8822c_txgapk_rf_restore(struct rtw_dev *rtwdev, u8 path)
1619 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__);
1621 if (path >= rtwdev->hal.rf_path_num)
1624 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RF_MODE, 0x3);
1625 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x0);
1626 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x0);
1629 static u32 rtw8822c_txgapk_cal_gain(struct rtw_dev *rtwdev, u32 gain, s8 offset)
1633 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__);
1635 if (_rtw8822c_txgapk_gain_valid(rtwdev, gain)) {
1637 rtw_dbg(rtwdev, RTW_DBG_RFK,
1646 rtw_dbg(rtwdev, RTW_DBG_RFK,
1653 static void rtw8822c_txgapk_write_tx_gain(struct rtw_dev *rtwdev)
1655 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk;
1660 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__);
1675 rtw_err(rtwdev, "[TXGAPK] unknown channel %d!!\n", channel);
1679 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1684 if (_rtw8822c_txgapk_gain_valid(rtwdev, v))
1692 if (_rtw8822c_txgapk_gain_valid(rtwdev, v)) {
1693 rtw_dbg(rtwdev, RTW_DBG_RFK,
1698 rtw_dbg(rtwdev, RTW_DBG_RFK,
1704 rtw_write_rf(rtwdev, path, RF_LUTWE2, RFREG_MASK, 0x10000);
1706 rtw_write_rf(rtwdev, path,
1709 tmp_3f = rtw8822c_txgapk_cal_gain(rtwdev,
1712 rtw_write_rf(rtwdev, path, RF_LUTWD0,
1715 rtw_dbg(rtwdev, RTW_DBG_RFK,
1719 rtw_write_rf(rtwdev, path, RF_LUTWE2, RFREG_MASK, 0x0);
1723 static void rtw8822c_txgapk_save_all_tx_gain_table(struct rtw_dev *rtwdev)
1725 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk;
1733 if (rtwdev->dm_info.dm_flags & BIT(RTW_DM_CAP_TXGAPK))
1736 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__);
1739 rtw_dbg(rtwdev, RTW_DBG_RFK,
1741 rtw8822c_txgapk_write_gain_bb_table(rtwdev);
1746 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1747 rf18 = rtw_read_rf(rtwdev, path, RF_CFGCH, RFREG_MASK);
1749 rtw_write32_mask(rtwdev,
1751 rtw_write_rf(rtwdev, path,
1753 rtw_write_rf(rtwdev, path,
1755 rtw_write_rf(rtwdev, path,
1757 rtw_write_rf(rtwdev, path,
1761 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC,
1763 v = rtw_read_rf(rtwdev, path,
1767 rtw_dbg(rtwdev, RTW_DBG_RFK,
1773 rtw_write_rf(rtwdev, path, RF_CFGCH, RFREG_MASK, rf18);
1774 rtw_write32_mask(rtwdev,
1778 rtw8822c_txgapk_write_gain_bb_table(rtwdev);
1782 static void rtw8822c_txgapk(struct rtw_dev *rtwdev)
1785 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk;
1789 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__);
1791 rtw8822c_txgapk_save_all_tx_gain_table(rtwdev);
1794 rtw_dbg(rtwdev, RTW_DBG_RFK,
1799 if (rtwdev->efuse.power_track_type >= 4 &&
1800 rtwdev->efuse.power_track_type <= 7) {
1801 rtw_dbg(rtwdev, RTW_DBG_RFK,
1806 rtw8822c_txgapk_backup_bb_reg(rtwdev, bb_reg,
1808 rtw8822c_txgapk_tx_pause(rtwdev);
1809 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1810 txgapk->channel = rtw_read_rf(rtwdev, path,
1812 rtw8822c_txgapk_bb_dpk(rtwdev, path);
1813 rtw8822c_txgapk_afe_dpk(rtwdev, path);
1814 rtw8822c_txgapk_calculate_offset(rtwdev, path);
1815 rtw8822c_txgapk_rf_restore(rtwdev, path);
1816 rtw8822c_txgapk_afe_dpk_restore(rtwdev, path);
1817 rtw8822c_txgapk_bb_dpk_restore(rtwdev, path);
1819 rtw8822c_txgapk_write_tx_gain(rtwdev);
1820 rtw8822c_txgapk_reload_bb_reg(rtwdev, bb_reg,
1824 static void rtw8822c_do_gapk(struct rtw_dev *rtwdev)
1826 struct rtw_dm_info *dm = &rtwdev->dm_info;
1829 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] feature disable!!!\n");
1832 rtw8822c_rfk_handshake(rtwdev, true);
1833 rtw8822c_txgapk(rtwdev);
1834 rtw8822c_rfk_handshake(rtwdev, false);
1837 static void rtw8822c_rf_init(struct rtw_dev *rtwdev)
1839 rtw8822c_rf_dac_cal(rtwdev);
1840 rtw8822c_rf_x2_check(rtwdev);
1841 rtw8822c_thermal_trim(rtwdev);
1842 rtw8822c_power_trim(rtwdev);
1843 rtw8822c_pa_bias(rtwdev);
1846 static void rtw8822c_pwrtrack_init(struct rtw_dev *rtwdev)
1848 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1858 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
1859 dm_info->thermal_meter_lck = rtwdev->efuse.thermal_meter_k;
1862 static void rtw8822c_phy_set_param(struct rtw_dev *rtwdev)
1864 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1865 struct rtw_hal *hal = &rtwdev->hal;
1874 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN,
1876 rtw_write8_set(rtwdev, REG_RF_CTRL,
1878 rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN);
1881 rtw_write32_mask(rtwdev, REG_DIS_DPD, DIS_DPD_MASK, DIS_DPD_RATEALL);
1884 rtw8822c_header_file_init(rtwdev, true);
1886 rtw_phy_load_tables(rtwdev);
1888 crystal_cap = rtwdev->efuse.crystal_cap & 0x7f;
1889 rtw_write32_mask(rtwdev, REG_ANAPAR_XTAL_0, 0xfffc00,
1893 rtw8822c_header_file_init(rtwdev, false);
1896 rtw8822c_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx,
1898 rtw_phy_init(rtwdev);
1900 cck_gi_u_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc000);
1901 cck_gi_u_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1aa8, 0xf0000);
1902 cck_gi_l_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc0);
1903 cck_gi_l_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1a70, 0x0f000000);
1908 rtw8822c_rf_init(rtwdev);
1909 rtw8822c_pwrtrack_init(rtwdev);
1911 rtw_bf_phy_init(rtwdev);
2003 static int rtw8822c_mac_init(struct rtw_dev *rtwdev)
2011 value8 = rtw_read8(rtwdev, REG_FWHW_TXQ_CTRL);
2013 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL, value8);
2014 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN);
2016 rtw_write16(rtwdev, REG_SPEC_SIFS, WLAN_SIFS_DUR_TUNE);
2017 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG);
2018 rtw_write16(rtwdev, REG_RESP_SIFS_CCK,
2020 rtw_write16(rtwdev, REG_RESP_SIFS_OFDM,
2023 rtw_write32(rtwdev, REG_DARFRC, WLAN_DATA_RATE_FB_CNT_1_4);
2024 rtw_write32(rtwdev, REG_DARFRCH, WLAN_DATA_RATE_FB_CNT_5_8);
2025 rtw_write32(rtwdev, REG_RARFRCH, WLAN_RTS_RATE_FB_CNT_5_8);
2026 rtw_write32(rtwdev, REG_ARFR0, WLAN_DATA_RATE_FB_RATE0);
2027 rtw_write32(rtwdev, REG_ARFRH0, WLAN_DATA_RATE_FB_RATE0_H);
2028 rtw_write32(rtwdev, REG_ARFR1_V1, WLAN_RTS_RATE_FB_RATE1);
2029 rtw_write32(rtwdev, REG_ARFRH1_V1, WLAN_RTS_RATE_FB_RATE1_H);
2030 rtw_write32(rtwdev, REG_ARFR4, WLAN_RTS_RATE_FB_RATE4);
2031 rtw_write32(rtwdev, REG_ARFRH4, WLAN_RTS_RATE_FB_RATE4_H);
2032 rtw_write32(rtwdev, REG_ARFR5, WLAN_RTS_RATE_FB_RATE5);
2033 rtw_write32(rtwdev, REG_ARFRH5, WLAN_RTS_RATE_FB_RATE5_H);
2035 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME);
2036 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
2038 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF));
2039 rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8));
2043 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32);
2044 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2,
2046 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH);
2047 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH);
2048 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH);
2049 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH);
2051 rtw_write8_clr(rtwdev, REG_LIFETIME_EN, BIT_BA_PARSER_EN);
2052 rtw_write32_clr(rtwdev, REG_RRSR, BITS_RRSR_RSC);
2055 rtw_write32(rtwdev, REG_EDCA_VO_PARAM, WLAN_EDCA_VO_PARAM);
2056 rtw_write32(rtwdev, REG_EDCA_VI_PARAM, WLAN_EDCA_VI_PARAM);
2057 rtw_write32(rtwdev, REG_EDCA_BE_PARAM, WLAN_EDCA_BE_PARAM);
2058 rtw_write32(rtwdev, REG_EDCA_BK_PARAM, WLAN_EDCA_BK_PARAM);
2059 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME);
2060 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8);
2061 rtw_write8_set(rtwdev, REG_RD_CTRL + 1,
2066 rtw_write32_clr(rtwdev, REG_AFE_CTRL1, BIT_MAC_CLK_SEL);
2067 rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED);
2068 rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED);
2070 rtw_write8_set(rtwdev, REG_MISC_CTRL,
2072 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0);
2073 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000);
2074 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME);
2075 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG);
2076 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG);
2078 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
2080 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME);
2081 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT);
2082 rtw_write8(rtwdev, REG_BCN_CTRL_CLINT0, WLAN_BCN_CTRL_CLT0);
2083 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
2084 rtw_write8(rtwdev, REG_BCN_MAX_ERR, WLAN_BCN_MAX_ERR);
2087 rtw_write32(rtwdev, REG_MAR, WLAN_MULTI_ADDR);
2088 rtw_write32(rtwdev, REG_MAR + 4, WLAN_MULTI_ADDR);
2089 rtw_write8(rtwdev, REG_BBPSF_CTRL + 2, WLAN_RESP_TXRATE);
2090 rtw_write8(rtwdev, REG_ACKTO, WLAN_ACK_TO);
2091 rtw_write8(rtwdev, REG_ACKTO_CCK, WLAN_ACK_TO_CCK);
2092 rtw_write16(rtwdev, REG_EIFS, WLAN_EIFS_DUR_TUNE);
2093 rtw_write8(rtwdev, REG_NAV_CTRL + 2, WLAN_NAV_MAX);
2094 rtw_write8(rtwdev, REG_WMAC_TRXPTCL_CTL_H + 2, WLAN_BAR_ACK_TYPE);
2095 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0);
2096 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2);
2097 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG);
2098 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512);
2099 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2);
2100 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1);
2101 rtw_write32_set(rtwdev, REG_GENERAL_OPTION, BIT_DUMMY_FCS_READY_MASK_EN);
2102 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2);
2103 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION_1, WLAN_MAC_OPT_NORM_FUNC1);
2106 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL + 2) & 0xF00F;
2109 rtw_write16(rtwdev, REG_RXPSF_CTRL + 2, value16);
2115 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16);
2116 rtw_write32(rtwdev, REG_RXPSF_TYPE_CTRL, 0xFFFFFFFF);
2118 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL);
2122 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16);
2123 rtw_write8_set(rtwdev, REG_SND_PTCL_CTRL,
2127 rtw_write32(rtwdev, REG_INT_MIG, WLAN_MAC_INT_MIG_CFG);
2151 static int rtw8822c_dump_fw_crash(struct rtw_dev *rtwdev)
2158 ret = rtw_dump_reg(rtwdev, 0x0, FWCD_SIZE_REG_8822C);
2161 ret = __dump_fw_8822c(rtwdev, DMEM);
2164 ret = __dump_fw_8822c(rtwdev, IMEM);
2167 ret = __dump_fw_8822c(rtwdev, EMEM);
2170 ret = __dump_fw_8822c(rtwdev, ROM);
2179 static void rtw8822c_rstb_3wire(struct rtw_dev *rtwdev, bool enable)
2182 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x1);
2183 rtw_write32_mask(rtwdev, REG_ANAPAR_A, BIT_ANAPAR_UPDATE, 0x1);
2184 rtw_write32_mask(rtwdev, REG_ANAPAR_B, BIT_ANAPAR_UPDATE, 0x1);
2186 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x0);
2190 static void rtw8822c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
2207 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
2238 rtw8822c_rstb_3wire(rtwdev, false);
2240 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x01);
2241 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, 0x1f, 0x12);
2242 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, 0xfffff, rf_rxbb);
2243 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x00);
2245 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x01);
2246 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWA, 0x1f, 0x12);
2247 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWD0, 0xfffff, rf_rxbb);
2248 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x00);
2250 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_reg18);
2251 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_reg18);
2253 rtw8822c_rstb_3wire(rtwdev, true);
2256 static void rtw8822c_toggle_igi(struct rtw_dev *rtwdev)
2260 igi = rtw_read32_mask(rtwdev, REG_RXIGI, 0x7f);
2261 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi - 2);
2262 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi - 2);
2263 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi);
2264 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi);
2267 static void rtw8822c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
2271 rtw_write32_clr(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT);
2272 rtw_write32_set(rtwdev, REG_TXF4, BIT(20));
2273 rtw_write32_clr(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN);
2274 rtw_write32_clr(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN);
2275 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0xF);
2279 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK,
2281 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK,
2283 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
2285 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
2289 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK,
2291 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK,
2293 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
2295 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
2300 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x969);
2302 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x96a);
2304 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x9aa);
2306 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x3da0);
2307 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD,
2309 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x6aa3);
2310 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xaa7b);
2311 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xf3d7);
2312 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 0x0);
2313 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD,
2315 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 0xffff);
2317 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x5284);
2318 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD,
2320 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x0a88);
2321 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xacc4);
2322 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xc8b2);
2323 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD,
2325 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD,
2327 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD,
2331 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3);
2333 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x1);
2335 rtw_write32_set(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN);
2336 rtw_write32_set(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN);
2337 rtw_write32_set(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT);
2338 rtw_write32_clr(rtwdev, REG_TXF4, BIT(20));
2339 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0x22);
2340 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3);
2342 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
2344 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
2347 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
2349 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
2352 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
2354 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
2359 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x494);
2361 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x493);
2363 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x453);
2365 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x452);
2367 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x412);
2369 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x411);
2374 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x19B);
2375 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
2376 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x0);
2377 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x7);
2378 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x6);
2379 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
2380 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
2381 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
2384 rtw_write32_mask(rtwdev, REG_CCKSB, BIT(4),
2386 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x5);
2387 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0);
2388 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00,
2390 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x1);
2391 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
2392 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1);
2395 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0xa);
2396 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0);
2397 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00,
2399 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x6);
2400 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1);
2403 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB);
2404 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
2405 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x1);
2406 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x4);
2407 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x4);
2408 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
2409 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
2410 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
2413 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB);
2414 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
2415 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x2);
2416 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x6);
2417 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x5);
2418 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
2419 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
2420 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
2425 static void rtw8822c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
2428 rtw8822c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
2429 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
2430 rtw8822c_set_channel_rf(rtwdev, channel, bw);
2431 rtw8822c_toggle_igi(rtwdev);
2434 static void rtw8822c_config_cck_rx_path(struct rtw_dev *rtwdev, u8 rx_path)
2437 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x0);
2438 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x0);
2440 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x1);
2441 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x1);
2445 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x0);
2447 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x5);
2449 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x1);
2452 static void rtw8822c_config_ofdm_rx_path(struct rtw_dev *rtwdev, u8 rx_path)
2455 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x0);
2456 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x0);
2457 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x0);
2458 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x0);
2459 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x0);
2461 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x1);
2462 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x1);
2463 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x1);
2464 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x1);
2465 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x1);
2468 rtw_write32_mask(rtwdev, 0x824, 0x0f000000, rx_path);
2469 rtw_write32_mask(rtwdev, 0x824, 0x000f0000, rx_path);
2472 static void rtw8822c_config_rx_path(struct rtw_dev *rtwdev, u8 rx_path)
2474 rtw8822c_config_cck_rx_path(rtwdev, rx_path);
2475 rtw8822c_config_ofdm_rx_path(rtwdev, rx_path);
2478 static void rtw8822c_config_cck_tx_path(struct rtw_dev *rtwdev, u8 tx_path,
2482 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8);
2484 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x4);
2487 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0xc);
2489 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8);
2491 rtw8822c_bb_reset(rtwdev);
2494 static void rtw8822c_config_ofdm_tx_path(struct rtw_dev *rtwdev, u8 tx_path,
2498 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x11);
2499 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0);
2501 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x12);
2502 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0);
2505 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x33);
2506 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0404);
2508 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x32);
2509 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0400);
2511 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x31);
2512 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0400);
2515 rtw8822c_bb_reset(rtwdev);
2518 static void rtw8822c_config_tx_path(struct rtw_dev *rtwdev, u8 tx_path,
2523 rtw8822c_config_cck_tx_path(rtwdev, tx_path_cck, is_tx2_path);
2524 rtw8822c_config_ofdm_tx_path(rtwdev, tx_path, tx_path_sel_1ss);
2525 rtw8822c_bb_reset(rtwdev);
2528 static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path,
2532 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x33312);
2534 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x11111);
2536 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x33312);
2538 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x11111);
2540 rtw8822c_config_rx_path(rtwdev, rx_path);
2541 rtw8822c_config_tx_path(rtwdev, tx_path, BB_PATH_A, BB_PATH_A,
2544 rtw8822c_toggle_igi(rtwdev);
2547 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status,
2550 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2579 channel = rtwdev->hal.current_channel;
2585 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) {
2596 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status,
2599 struct rtw_path_div *p_div = &rtwdev->dm_path_div;
2600 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2643 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) {
2666 rtw_phy_parsing_cfo(rtwdev, pkt_stat);
2669 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
2678 query_phy_status_page0(rtwdev, phy_status, pkt_stat);
2681 query_phy_status_page1(rtwdev, phy_status, pkt_stat);
2684 rtw_warn(rtwdev, "unused phy status page (%d)\n", page);
2689 static void rtw8822c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc,
2694 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz;
2725 query_phy_status(rtwdev, phy_status, pkt_stat);
2728 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status);
2732 rtw8822c_set_write_tx_power_ref(struct rtw_dev *rtwdev, u8 *tx_pwr_ref_cck,
2735 struct rtw_hal *hal = &rtwdev->hal;
2741 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0);
2742 rtw_write32_mask(rtwdev, txref_cck[path], 0x7f0000,
2746 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0);
2747 rtw_write32_mask(rtwdev, txref_ofdm[path], 0x1fc00,
2752 static void rtw8822c_set_tx_power_diff(struct rtw_dev *rtwdev, u8 rate,
2769 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0x0);
2770 rtw_write32_mask(rtwdev, offset_txagc + rate_idx, MASKDWORD,
2774 static void rtw8822c_set_tx_power_index(struct rtw_dev *rtwdev)
2776 struct rtw_hal *hal = &rtwdev->hal;
2786 rtw8822c_set_write_tx_power_ref(rtwdev, pwr_ref_cck, pwr_ref_ofdm);
2801 rtw8822c_set_tx_power_diff(rtwdev, rate - 3,
2807 static int rtw8822c_set_antenna(struct rtw_dev *rtwdev,
2811 struct rtw_hal *hal = &rtwdev->hal;
2819 rtw_warn(rtwdev, "unsupported tx path 0x%x\n", antenna_tx);
2829 rtw_warn(rtwdev, "unsupported rx path 0x%x\n", antenna_rx);
2836 rtw8822c_config_trx_mode(rtwdev, antenna_tx, antenna_rx, false);
2841 static void rtw8822c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)
2845 ldo_pwr = rtw_read8(rtwdev, REG_ANAPARLDO_POW_MAC);
2847 rtw_write8(rtwdev, REG_ANAPARLDO_POW_MAC, ldo_pwr);
2850 static void rtw8822c_false_alarm_statistics(struct rtw_dev *rtwdev)
2852 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2862 cck_enable = rtw_read32(rtwdev, REG_ENCCK) & BIT_CCK_BLK_EN;
2863 cck_fa_cnt = rtw_read16(rtwdev, REG_CCK_FACNT);
2865 ofdm_fa_cnt1 = rtw_read32(rtwdev, REG_OFDM_FACNT1);
2866 ofdm_fa_cnt2 = rtw_read32(rtwdev, REG_OFDM_FACNT2);
2867 ofdm_fa_cnt3 = rtw_read32(rtwdev, REG_OFDM_FACNT3);
2868 ofdm_fa_cnt4 = rtw_read32(rtwdev, REG_OFDM_FACNT4);
2869 ofdm_fa_cnt5 = rtw_read32(rtwdev, REG_OFDM_FACNT5);
2888 crc32_cnt = rtw_read32(rtwdev, 0x2c04);
2891 crc32_cnt = rtw_read32(rtwdev, 0x2c14);
2894 crc32_cnt = rtw_read32(rtwdev, 0x2c10);
2897 crc32_cnt = rtw_read32(rtwdev, 0x2c0c);
2901 cca32_cnt = rtw_read32(rtwdev, 0x2c08);
2908 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 0);
2909 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 2);
2910 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 0);
2911 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 2);
2914 rtw_write32_clr(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN);
2915 rtw_write32_set(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST);
2916 rtw_write32_clr(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST);
2917 rtw_write32_set(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN);
2920 static void rtw8822c_do_lck(struct rtw_dev *rtwdev)
2924 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_CTRL, RFREG_MASK, 0x80010);
2925 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_PFD, RFREG_MASK, 0x1F0FA);
2927 rtw_write_rf(rtwdev, RF_PATH_A, RF_AAC_CTRL, RFREG_MASK, 0x80000);
2928 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_AAC, RFREG_MASK, 0x80001);
2930 true, rtwdev, RF_PATH_A, RF_AAC_CTRL, 0x1000);
2931 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_PFD, RFREG_MASK, 0x1F0F8);
2932 rtw_write_rf(rtwdev, RF_PATH_B, RF_SYN_CTRL, RFREG_MASK, 0x80010);
2934 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x0f000);
2935 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x4f000);
2937 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x0f000);
2940 static void rtw8822c_do_iqk(struct rtw_dev *rtwdev)
2947 rtw_fw_do_iqk(rtwdev, ¶);
2950 20000, 300000, false, rtwdev, REG_RPT_CIP);
2952 rtw_warn(rtwdev, "failed to poll iqk status bit\n");
2954 rtw_write8(rtwdev, REG_IQKSTAT, 0x0);
2958 static void rtw8822c_coex_cfg_init(struct rtw_dev *rtwdev)
2961 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
2965 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5);
2968 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1);
2971 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);
2972 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS);
2975 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN);
2977 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN);
2979 rtw_write16_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY);
2981 rtw_write8_clr(rtwdev, REG_DUMMY_PAGE4_V1, BIT_BTCCA_CTRL);
2984 rtw_write_rf(rtwdev, RF_PATH_B, RF_MODOPT, 0xfffff, 0x40000);
2987 static void rtw8822c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
2989 struct rtw_coex *coex = &rtwdev->coex;
2991 struct rtw_efuse *efuse = &rtwdev->efuse;
3008 rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, rf_0x1);
3019 rtw_write8_mask(rtwdev, REG_ANAPAR + 2,
3022 rtw_write8_mask(rtwdev, REG_ANAPAR + 2,
3024 rtw_write8_mask(rtwdev, REG_RSTB_SEL + 1,
3026 rtw_write8_mask(rtwdev, REG_RSTB_SEL + 3,
3033 rtw_write8_mask(rtwdev, REG_IGN_GNTBT4,
3040 rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1,
3042 rtw_write8_mask(rtwdev, REG_NOMASK_TXBT,
3047 rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1,
3049 rtw_write8_mask(rtwdev, REG_NOMASK_TXBT,
3052 rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1,
3057 rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1,
3060 rtw_write8_mask(rtwdev, REG_NOMASK_TXBT,
3066 static void rtw8822c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev)
3068 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0);
3069 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0);
3070 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT_FSPI_EN >> 16, 0);
3071 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0);
3072 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT_DBG_GNT_WL_BT >> 24, 0);
3075 static void rtw8822c_coex_cfg_rfe_type(struct rtw_dev *rtwdev)
3077 struct rtw_coex *coex = &rtwdev->coex;
3079 struct rtw_efuse *efuse = &rtwdev->efuse;
3081 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option;
3093 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0);
3094 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff);
3095 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff);
3098 static void rtw8822c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
3100 struct rtw_coex *coex = &rtwdev->coex;
3109 static void rtw8822c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
3111 struct rtw_coex *coex = &rtwdev->coex;
3120 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table On!\n");
3123 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, RFREG_MASK, 0x22);
3124 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, RFREG_MASK, 0x36);
3125 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, RFREG_MASK, 0x22);
3126 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, RFREG_MASK, 0x36);
3129 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table Off!\n");
3132 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, RFREG_MASK, 0x20);
3133 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, RFREG_MASK, 0x0);
3134 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, RFREG_MASK, 0x20);
3135 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, RFREG_MASK, 0x0);
3139 static void rtw8822c_bf_enable_bfee_su(struct rtw_dev *rtwdev,
3146 rtw_bf_enable_bfee_su(rtwdev, vif, bfee);
3148 tmp6dc = rtw_read32(rtwdev, REG_BBPSF_CTRL) |
3152 rtw_write32(rtwdev, REG_BBPSF_CTRL, tmp6dc | BIT(12));
3154 rtw_write32(rtwdev, REG_BBPSF_CTRL, tmp6dc & ~BIT(12));
3156 rtw_write32(rtwdev, REG_CSI_RRSR, 0x550);
3159 static void rtw8822c_bf_config_bfee_su(struct rtw_dev *rtwdev,
3164 rtw8822c_bf_enable_bfee_su(rtwdev, vif, bfee);
3166 rtw_bf_remove_bfee_su(rtwdev, bfee);
3169 static void rtw8822c_bf_config_bfee_mu(struct rtw_dev *rtwdev,
3174 rtw_bf_enable_bfee_mu(rtwdev, vif, bfee);
3176 rtw_bf_remove_bfee_mu(rtwdev, bfee);
3179 static void rtw8822c_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif,
3183 rtw8822c_bf_config_bfee_su(rtwdev, vif, bfee, enable);
3185 rtw8822c_bf_config_bfee_mu(rtwdev, vif, bfee, enable);
3187 rtw_warn(rtwdev, "wrong bfee role\n");
3196 void rtw8822c_parse_tbl_dpk(struct rtw_dev *rtwdev,
3205 rtw_write32_mask(rtwdev, p->addr, p->bitmask, p->data);
3208 static void rtw8822c_dpk_set_gnt_wl(struct rtw_dev *rtwdev, bool is_before_k)
3210 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3213 dpk_info->gnt_control = rtw_read32(rtwdev, 0x70);
3214 dpk_info->gnt_value = rtw_coex_read_indirect_reg(rtwdev, 0x38);
3215 rtw_write32_mask(rtwdev, 0x70, BIT(26), 0x1);
3216 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKBYTE1, 0x77);
3218 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKDWORD,
3220 rtw_write32(rtwdev, 0x70, dpk_info->gnt_control);
3225 rtw8822c_dpk_restore_registers(struct rtw_dev *rtwdev, u32 reg_num,
3228 rtw_restore_reg(rtwdev, bckp, reg_num);
3229 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3230 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0x4);
3234 rtw8822c_dpk_backup_registers(struct rtw_dev *rtwdev, u32 *reg,
3242 bckp[i].val = rtw_read32(rtwdev, reg[i]);
3246 static void rtw8822c_dpk_backup_rf_registers(struct rtw_dev *rtwdev,
3253 rf_reg_bak[i][RF_PATH_A] = rtw_read_rf(rtwdev, RF_PATH_A,
3255 rf_reg_bak[i][RF_PATH_B] = rtw_read_rf(rtwdev, RF_PATH_B,
3260 static void rtw8822c_dpk_reload_rf_registers(struct rtw_dev *rtwdev,
3267 rtw_write_rf(rtwdev, RF_PATH_A, rf_reg[i], RFREG_MASK,
3269 rtw_write_rf(rtwdev, RF_PATH_B, rf_reg[i], RFREG_MASK,
3274 static void rtw8822c_dpk_information(struct rtw_dev *rtwdev)
3276 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3280 reg = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
3288 static void rtw8822c_dpk_rxbb_dc_cal(struct rtw_dev *rtwdev, u8 path)
3290 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800);
3292 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84801);
3294 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800);
3297 static u8 rtw8822c_dpk_dc_corr_check(struct rtw_dev *rtwdev, u8 path)
3302 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000900f0);
3303 dc_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16));
3304 dc_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(11, 0));
3311 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0);
3312 corr_idx = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(7, 0));
3313 rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(15, 8));
3322 static void rtw8822c_dpk_tx_pause(struct rtw_dev *rtwdev)
3327 rtw_write8(rtwdev, 0x522, 0xff);
3328 rtw_write32_mask(rtwdev, 0x1e70, 0xf, 0x2);
3331 reg_a = (u8)rtw_read_rf(rtwdev, RF_PATH_A, 0x00, 0xf0000);
3332 reg_b = (u8)rtw_read_rf(rtwdev, RF_PATH_B, 0x00, 0xf0000);
3338 static void rtw8822c_dpk_mac_bb_setting(struct rtw_dev *rtwdev)
3340 rtw8822c_dpk_tx_pause(rtwdev);
3341 rtw_load_table(rtwdev, &rtw8822c_dpk_mac_bb_tbl);
3344 static void rtw8822c_dpk_afe_setting(struct rtw_dev *rtwdev, bool is_do_dpk)
3347 rtw_load_table(rtwdev, &rtw8822c_dpk_afe_is_dpk_tbl);
3349 rtw_load_table(rtwdev, &rtw8822c_dpk_afe_no_dpk_tbl);
3352 static void rtw8822c_dpk_pre_setting(struct rtw_dev *rtwdev)
3356 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
3357 rtw_write_rf(rtwdev, path, RF_RXAGC_OFFSET, RFREG_MASK, 0x0);
3358 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1));
3359 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G)
3360 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f100000);
3362 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f0d0000);
3363 rtw_write32_mask(rtwdev, REG_DPD_LUT0, BIT_GLOSS_DB, 0x4);
3364 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x3);
3366 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3367 rtw_write32(rtwdev, REG_DPD_CTL11, 0x3b23170b);
3368 rtw_write32(rtwdev, REG_DPD_CTL12, 0x775f5347);
3371 static u32 rtw8822c_dpk_rf_setting(struct rtw_dev *rtwdev, u8 path)
3375 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x50017);
3376 ori_txbb = rtw_read_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK);
3378 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1);
3379 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_PWR_TRIM, 0x1);
3380 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_BB_GAIN, 0x0);
3381 rtw_write_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK, ori_txbb);
3383 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G) {
3384 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_RF_GAIN, 0x1);
3385 rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x0);
3387 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x0);
3388 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_ATT, 0x6);
3389 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_SW, 0x1);
3390 rtw_write_rf(rtwdev, path, RF_RXA_MIX_GAIN, BIT_RXA_MIX_GAIN, 0);
3393 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf);
3394 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1);
3395 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0);
3397 if (rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80)
3398 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x2);
3400 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x1);
3402 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT(1), 0x1);
3409 static u16 rtw8822c_dpk_get_cmd(struct rtw_dev *rtwdev, u8 action, u8 path)
3412 u8 bw = rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80 ? 2 : 0;
3434 static u8 rtw8822c_dpk_one_shot(struct rtw_dev *rtwdev, u8 path, u8 action)
3439 rtw8822c_dpk_set_gnt_wl(rtwdev, true);
3442 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x1);
3443 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x0);
3444 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0);
3446 if (!check_hw_ready(rtwdev, REG_STAT_RPT, BIT(31), 0x1)) {
3448 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n");
3451 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
3453 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9);
3455 dpk_cmd = rtw8822c_dpk_get_cmd(rtwdev, action, path);
3456 rtw_write32(rtwdev, REG_NCTL0, dpk_cmd);
3457 rtw_write32(rtwdev, REG_NCTL0, dpk_cmd + 1);
3459 if (!check_hw_ready(rtwdev, 0x2d9c, 0xff, 0x55)) {
3461 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n");
3463 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
3465 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0);
3468 rtw8822c_dpk_set_gnt_wl(rtwdev, false);
3470 rtw_write8(rtwdev, 0x1b10, 0x0);
3475 static u16 rtw8822c_dpk_dgain_read(struct rtw_dev *rtwdev, u8 path)
3479 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3480 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, 0x00ff0000, 0x0);
3482 dgain = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16));
3487 static u8 rtw8822c_dpk_thermal_read(struct rtw_dev *rtwdev, u8 path)
3489 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1);
3490 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x0);
3491 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1);
3494 return (u8)rtw_read_rf(rtwdev, path, RF_T_METER, 0x0007e);
3497 static u32 rtw8822c_dpk_pas_read(struct rtw_dev *rtwdev, u8 path)
3501 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1));
3502 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0);
3503 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060001);
3504 rtw_write32(rtwdev, 0x1b4c, 0x00000000);
3505 rtw_write32(rtwdev, 0x1b4c, 0x00080000);
3507 q_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD);
3508 i_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD);
3515 rtw_write32(rtwdev, 0x1b4c, 0x00000000);
3546 static u8 rtw8822c_dpk_gainloss_result(struct rtw_dev *rtwdev, u8 path)
3550 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3551 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x1);
3552 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060000);
3554 result = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, 0x000000f0);
3556 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0);
3561 static u8 rtw8822c_dpk_agc_gain_chk(struct rtw_dev *rtwdev, u8 path,
3567 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC);
3568 dgain = rtw8822c_dpk_dgain_read(rtwdev, path);
3578 static u8 rtw8822c_dpk_agc_loss_chk(struct rtw_dev *rtwdev, u8 path)
3582 loss = rtw8822c_dpk_pas_read(rtwdev, path);
3605 static u8 rtw8822c_gain_check_state(struct rtw_dev *rtwdev,
3610 data->txbb = (u8)rtw_read_rf(rtwdev, data->path, RF_TX_GAIN,
3612 data->pga = (u8)rtw_read_rf(rtwdev, data->path, RF_MODE_TRXAGC,
3620 state = rtw8822c_dpk_agc_gain_chk(rtwdev, data->path,
3635 static u8 rtw8822c_gain_large_state(struct rtw_dev *rtwdev,
3641 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc);
3643 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0);
3650 static u8 rtw8822c_gain_less_state(struct rtw_dev *rtwdev,
3656 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc);
3658 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf);
3665 static u8 rtw8822c_gl_state(struct rtw_dev *rtwdev,
3678 rtw_write_rf(rtwdev, data->path, RF_TX_GAIN, BIT_GAIN_TXBB, data->txbb);
3684 static u8 rtw8822c_gl_large_state(struct rtw_dev *rtwdev,
3687 return rtw8822c_gl_state(rtwdev, data, 1);
3690 static u8 rtw8822c_gl_less_state(struct rtw_dev *rtwdev,
3693 return rtw8822c_gl_state(rtwdev, data, 0);
3696 static u8 rtw8822c_loss_check_state(struct rtw_dev *rtwdev,
3702 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_GAIN_LOSS);
3703 state = rtw8822c_dpk_agc_loss_chk(rtwdev, path);
3708 static u8 (*dpk_state[])(struct rtw_dev *rtwdev,
3714 static u8 rtw8822c_dpk_pas_agc(struct rtw_dev *rtwdev, u8 path,
3718 u8 (*func)(struct rtw_dev *rtwdev, struct rtw8822c_dpk_data *data);
3727 state = func(rtwdev, &data);
3735 static bool rtw8822c_dpk_coef_iq_check(struct rtw_dev *rtwdev,
3745 static u32 rtw8822c_dpk_coef_transfer(struct rtw_dev *rtwdev)
3750 reg = rtw_read32(rtwdev, REG_STAT_RPT);
3752 coef_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD) & 0x1fff;
3753 coef_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD) & 0x1fff;
3769 static void rtw8822c_dpk_coef_tbl_apply(struct rtw_dev *rtwdev, u8 path)
3771 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3775 rtw_write32(rtwdev, REG_RXSRAM_CTL,
3777 dpk_info->coef[path][i] = rtw8822c_dpk_coef_transfer(rtwdev);
3781 static void rtw8822c_dpk_get_coef(struct rtw_dev *rtwdev, u8 path)
3783 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c);
3786 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x0);
3787 rtw_write32(rtwdev, REG_DPD_CTL0_S0, 0x30000080);
3789 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x1);
3790 rtw_write32(rtwdev, REG_DPD_CTL0_S1, 0x30000080);
3793 rtw8822c_dpk_coef_tbl_apply(rtwdev, path);
3796 static u8 rtw8822c_dpk_coef_read(struct rtw_dev *rtwdev, u8 path)
3798 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3806 if (rtw8822c_dpk_coef_iq_check(rtwdev, coef_i, coef_q)) {
3814 static void rtw8822c_dpk_coef_write(struct rtw_dev *rtwdev, u8 path, u8 result)
3816 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3821 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c);
3822 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0);
3833 rtw_write32(rtwdev, reg[path] + addr * 4, coef);
3837 static void rtw8822c_dpk_fill_result(struct rtw_dev *rtwdev, u32 dpk_txagc,
3840 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3842 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3845 rtw_write8(rtwdev, REG_DPD_AGC, (u8)(dpk_txagc - 6));
3847 rtw_write8(rtwdev, REG_DPD_AGC, 0x00);
3850 dpk_info->dpk_txagc[path] = rtw_read8(rtwdev, REG_DPD_AGC);
3852 rtw8822c_dpk_coef_write(rtwdev, path, result);
3855 static u32 rtw8822c_dpk_gainloss(struct rtw_dev *rtwdev, u8 path)
3857 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3860 ori_txbb = rtw8822c_dpk_rf_setting(rtwdev, path);
3861 ori_txagc = (u8)rtw_read_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_TXAGC);
3863 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path);
3864 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC);
3865 rtw8822c_dpk_dgain_read(rtwdev, path);
3867 if (rtw8822c_dpk_dc_corr_check(rtwdev, path)) {
3868 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path);
3869 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC);
3870 rtw8822c_dpk_dc_corr_check(rtwdev, path);
3873 t1 = rtw8822c_dpk_thermal_read(rtwdev, path);
3874 tx_bb = rtw8822c_dpk_pas_agc(rtwdev, path, false, true);
3875 tx_agc_search = rtw8822c_dpk_gainloss_result(rtwdev, path);
3882 rtw_write_rf(rtwdev, path, RF_TX_GAIN, BIT_GAIN_TXBB, tx_bb);
3886 t2 = rtw8822c_dpk_thermal_read(rtwdev, path);
3893 static u8 rtw8822c_dpk_by_path(struct rtw_dev *rtwdev, u32 tx_agc, u8 path)
3897 result = rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DO_DPK);
3899 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3901 result = result | (u8)rtw_read32_mask(rtwdev, REG_DPD_CTL1_S0, BIT(26));
3903 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x33e14);
3905 rtw8822c_dpk_get_coef(rtwdev, path);
3910 static void rtw8822c_dpk_cal_gs(struct rtw_dev *rtwdev, u8 path)
3912 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3915 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3916 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_BYPASS_DPD, 0x0);
3917 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
3918 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9);
3919 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x1);
3920 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3921 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0xf);
3924 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF,
3926 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN, 0x1);
3928 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF,
3930 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN, 0x1);
3934 rtw_write32(rtwdev, REG_DPD_CTL16, 0x80001310);
3935 rtw_write32(rtwdev, REG_DPD_CTL16, 0x00001310);
3936 rtw_write32(rtwdev, REG_DPD_CTL16, 0x810000db);
3937 rtw_write32(rtwdev, REG_DPD_CTL16, 0x010000db);
3938 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428);
3939 rtw_write32(rtwdev, REG_DPD_CTL15,
3942 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8200190c);
3943 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0200190c);
3944 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8301ee14);
3945 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0301ee14);
3946 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428);
3947 rtw_write32(rtwdev, REG_DPD_CTL15,
3951 rtw_write32_mask(rtwdev, REG_DPD_CTL0, MASKBYTE3, 0x8 | path);
3953 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_CAL_PWR);
3955 rtw_write32_mask(rtwdev, REG_DPD_CTL15, MASKBYTE3, 0x0);
3956 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3957 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0);
3958 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x0);
3959 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3962 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 0x5b);
3964 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 0x5b);
3966 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0);
3968 tmp_gs = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, BIT_RPT_DGAIN);
3973 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, tmp_gs);
3975 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, tmp_gs);
3980 static void rtw8822c_dpk_cal_coef1(struct rtw_dev *rtwdev)
3982 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3987 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c);
3988 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0);
3989 rtw_write32(rtwdev, REG_NCTL0, 0x00001148);
3990 rtw_write32(rtwdev, REG_NCTL0, 0x00001149);
3992 check_hw_ready(rtwdev, 0x2d9c, MASKBYTE0, 0x55);
3994 rtw_write8(rtwdev, 0x1b10, 0x0);
3995 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c);
3997 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
4000 rtw_write32_mask(rtwdev, 0x1b18 + offset[path], MASKHWORD,
4002 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path],
4004 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path],
4006 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path],
4008 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0 + offset[path],
4013 static void rtw8822c_dpk_on(struct rtw_dev *rtwdev, u8 path)
4015 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
4017 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DPK_ON);
4019 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
4020 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
4023 rtw8822c_dpk_cal_gs(rtwdev, path);
4026 static bool rtw8822c_dpk_check_pass(struct rtw_dev *rtwdev, bool is_fail,
4032 if (rtw8822c_dpk_coef_read(rtwdev, path))
4040 rtw8822c_dpk_fill_result(rtwdev, dpk_txagc, path, result);
4045 static void rtw8822c_dpk_result_reset(struct rtw_dev *rtwdev)
4047 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
4050 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
4052 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
4054 rtw_write32_mask(rtwdev, 0x1b58, 0x0000007f, 0x0);
4060 dpk_info->thermal_dpk[path] = rtw8822c_dpk_thermal_read(rtwdev,
4065 static void rtw8822c_dpk_calibrate(struct rtw_dev *rtwdev, u8 path)
4067 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
4071 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] s%d dpk start\n", path);
4073 dpk_txagc = rtw8822c_dpk_gainloss(rtwdev, path);
4075 dpk_fail = rtw8822c_dpk_by_path(rtwdev, dpk_txagc, path);
4077 if (!rtw8822c_dpk_check_pass(rtwdev, dpk_fail, dpk_txagc, path))
4078 rtw_err(rtwdev, "failed to do dpk calibration\n");
4080 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] s%d dpk finish\n", path);
4086 static void rtw8822c_dpk_path_select(struct rtw_dev *rtwdev)
4088 rtw8822c_dpk_calibrate(rtwdev, RF_PATH_A);
4089 rtw8822c_dpk_calibrate(rtwdev, RF_PATH_B);
4090 rtw8822c_dpk_on(rtwdev, RF_PATH_A);
4091 rtw8822c_dpk_on(rtwdev, RF_PATH_B);
4092 rtw8822c_dpk_cal_coef1(rtwdev);
4095 static void rtw8822c_dpk_enable_disable(struct rtw_dev *rtwdev)
4097 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
4100 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
4102 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN,
4104 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN,
4108 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, mask, 0x0);
4109 rtw_write8(rtwdev, REG_DPD_CTL0_S0, dpk_info->dpk_gs[RF_PATH_A]);
4112 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, mask, 0x0);
4113 rtw_write8(rtwdev, REG_DPD_CTL0_S1, dpk_info->dpk_gs[RF_PATH_B]);
4117 static void rtw8822c_dpk_reload_data(struct rtw_dev *rtwdev)
4119 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
4127 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
4128 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
4131 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f100000);
4133 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f0d0000);
4135 rtw_write8(rtwdev, REG_DPD_AGC, dpk_info->dpk_txagc[path]);
4137 rtw8822c_dpk_coef_write(rtwdev, path,
4140 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DPK_ON);
4142 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
4145 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF,
4148 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF,
4151 rtw8822c_dpk_cal_coef1(rtwdev);
4154 static bool rtw8822c_dpk_reload(struct rtw_dev *rtwdev)
4156 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
4161 channel = (u8)(rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK) & 0xff);
4164 rtw_dbg(rtwdev, RTW_DBG_RFK,
4166 rtw8822c_dpk_reload_data(rtwdev);
4173 static void rtw8822c_do_dpk(struct rtw_dev *rtwdev)
4175 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
4187 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] Skip DPK due to DPD PWR off\n");
4189 } else if (rtw8822c_dpk_reload(rtwdev)) {
4196 rtw8822c_dpk_information(rtwdev);
4198 rtw8822c_dpk_backup_registers(rtwdev, bb_reg, DPK_BB_REG_NUM, bckp);
4199 rtw8822c_dpk_backup_rf_registers(rtwdev, rf_reg, rf_reg_backup);
4201 rtw8822c_dpk_mac_bb_setting(rtwdev);
4202 rtw8822c_dpk_afe_setting(rtwdev, true);
4203 rtw8822c_dpk_pre_setting(rtwdev);
4204 rtw8822c_dpk_result_reset(rtwdev);
4205 rtw8822c_dpk_path_select(rtwdev);
4206 rtw8822c_dpk_afe_setting(rtwdev, false);
4207 rtw8822c_dpk_enable_disable(rtwdev);
4209 rtw8822c_dpk_reload_rf_registers(rtwdev, rf_reg, rf_reg_backup);
4210 for (path = 0; path < rtwdev->hal.rf_path_num; path++)
4211 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path);
4212 rtw8822c_dpk_restore_registers(rtwdev, DPK_BB_REG_NUM, bckp);
4215 static void rtw8822c_phy_calibration(struct rtw_dev *rtwdev)
4217 rtw8822c_rfk_power_save(rtwdev, false);
4218 rtw8822c_do_gapk(rtwdev);
4219 rtw8822c_do_iqk(rtwdev);
4220 rtw8822c_do_dpk(rtwdev);
4221 rtw8822c_rfk_power_save(rtwdev, true);
4224 static void rtw8822c_dpk_track(struct rtw_dev *rtwdev)
4226 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
4235 thermal_value[path] = rtw8822c_dpk_thermal_read(rtwdev, path);
4247 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
4249 rtw_write32_mask(rtwdev, 0x1b58, GENMASK(6, 0),
4257 static void rtw8822c_set_crystal_cap_reg(struct rtw_dev *rtwdev, u8 crystal_cap)
4259 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4265 rtw_write32_mask(rtwdev, REG_ANAPAR_XTAL_0, BIT_XCAP_0, val);
4268 static void rtw8822c_set_crystal_cap(struct rtw_dev *rtwdev, u8 crystal_cap)
4270 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4276 rtw8822c_set_crystal_cap_reg(rtwdev, crystal_cap);
4279 static void rtw8822c_cfo_tracking_reset(struct rtw_dev *rtwdev)
4281 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4286 if (cfo->crystal_cap > rtwdev->efuse.crystal_cap)
4287 rtw8822c_set_crystal_cap(rtwdev, cfo->crystal_cap - 1);
4288 else if (cfo->crystal_cap < rtwdev->efuse.crystal_cap)
4289 rtw8822c_set_crystal_cap(rtwdev, cfo->crystal_cap + 1);
4292 static void rtw8822c_cfo_init(struct rtw_dev *rtwdev)
4294 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4297 cfo->crystal_cap = rtwdev->efuse.crystal_cap;
4302 static s32 rtw8822c_cfo_calc_avg(struct rtw_dev *rtwdev, u8 path_num)
4304 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4328 static void rtw8822c_cfo_need_adjust(struct rtw_dev *rtwdev, s32 cfo_avg)
4330 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4341 if (!rtw_coex_disabled(rtwdev)) {
4343 rtw8822c_set_crystal_cap(rtwdev, rtwdev->efuse.crystal_cap);
4347 static void rtw8822c_cfo_track(struct rtw_dev *rtwdev)
4349 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4351 u8 path_num = rtwdev->hal.rf_path_num;
4355 if (rtwdev->sta_cnt != 1) {
4356 rtw8822c_cfo_tracking_reset(rtwdev);
4364 cfo_avg = rtw8822c_cfo_calc_avg(rtwdev, path_num);
4365 rtw8822c_cfo_need_adjust(rtwdev, cfo_avg);
4374 rtw8822c_set_crystal_cap(rtwdev, (u8)crystal_cap);
4395 rtw8822c_phy_cck_pd_set_reg(struct rtw_dev *rtwdev,
4403 pd = rtw_read32_mask(rtwdev,
4406 cs = rtw_read32_mask(rtwdev,
4417 rtw_write32_mask(rtwdev,
4421 rtw_write32_mask(rtwdev,
4426 rtw_dbg(rtwdev, RTW_DBG_PHY,
4428 rtw_is_assoc(rtwdev), bw, nrx, cs, pd);
4431 static void rtw8822c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl)
4433 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4439 nrx = (u8)rtw_read32_mask(rtwdev, 0x1a2c, 0x60000);
4440 bw = (u8)rtw_read32_mask(rtwdev, 0x9b0, 0xc);
4442 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d) bw=%d nr=%d cck_fa_avg=%d\n",
4454 rtw8822c_phy_cck_pd_set_reg(rtwdev,
4462 static void rtw8822c_pwrtrack_set(struct rtw_dev *rtwdev, u8 rf_path)
4464 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4468 rtw_write32_mask(rtwdev, 0x18a0, PWR_TRACK_MASK,
4472 rtw_write32_mask(rtwdev, 0x41a0, PWR_TRACK_MASK,
4480 static void rtw8822c_pwr_track_stats(struct rtw_dev *rtwdev, u8 path)
4484 if (rtwdev->efuse.thermal_meter[path] == 0xff)
4487 thermal_value = rtw_read_rf(rtwdev, path, RF_T_METER, 0x7e);
4488 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, path);
4491 static void rtw8822c_pwr_track_path(struct rtw_dev *rtwdev,
4495 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4498 delta = rtw_phy_pwrtrack_get_delta(rtwdev, path);
4500 rtw_phy_pwrtrack_get_pwridx(rtwdev, swing_table, path, path,
4502 rtw8822c_pwrtrack_set(rtwdev, path);
4505 static void __rtw8822c_pwr_track(struct rtw_dev *rtwdev)
4510 rtw_phy_config_swing_table(rtwdev, &swing_table);
4512 for (i = 0; i < rtwdev->hal.rf_path_num; i++)
4513 rtw8822c_pwr_track_stats(rtwdev, i);
4514 if (rtw_phy_pwrtrack_need_lck(rtwdev))
4515 rtw8822c_do_lck(rtwdev);
4516 for (i = 0; i < rtwdev->hal.rf_path_num; i++)
4517 rtw8822c_pwr_track_path(rtwdev, &swing_table, i);
4520 static void rtw8822c_pwr_track(struct rtw_dev *rtwdev)
4522 struct rtw_efuse *efuse = &rtwdev->efuse;
4523 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4529 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01);
4530 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x00);
4531 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01);
4533 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01);
4534 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x00);
4535 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01);
4541 __rtw8822c_pwr_track(rtwdev);
4545 static void rtw8822c_adaptivity_init(struct rtw_dev *rtwdev)
4547 rtw_phy_set_edcca_th(rtwdev, RTW8822C_EDCCA_MAX, RTW8822C_EDCCA_MAX);
4550 rtw_write32_clr(rtwdev, REG_TX_PTCL_CTRL, BIT_DIS_EDCCA);
4551 rtw_write32_set(rtwdev, REG_RD_CTRL, BIT_EDCCA_MSK_CNTDOWN_EN);
4554 rtw_write32_clr(rtwdev, REG_EDCCA_DECISION, BIT_EDCCA_OPTION);
4557 static void rtw8822c_adaptivity(struct rtw_dev *rtwdev)
4559 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
4575 rtw_phy_set_edcca_th(rtwdev, l2h, h2l);
4578 static void rtw8822c_fill_txdesc_checksum(struct rtw_dev *rtwdev,
4582 const struct rtw_chip_info *chip = rtwdev->chip;