Lines Matching refs:path
111 u32 path, i;
126 for (path = 0; path < DACK_PATH_8822C; path++) {
129 val = rtw_read_rf(rtwdev, path, reg, RFREG_MASK);
130 backup_rf[path * i + i].reg = reg;
131 backup_rf[path * i + i].val = val;
140 u32 path, i;
146 for (path = 0; path < DACK_PATH_8822C; path++) {
148 val = backup_rf[path * i + i].val;
149 reg = backup_rf[path * i + i].reg;
150 rtw_write_rf(rtwdev, path, reg, RFREG_MASK, val);
235 static u32 rtw8822c_get_path_write_addr(u8 path)
239 switch (path) {
254 static u32 rtw8822c_get_path_read_addr(u8 path)
258 switch (path) {
370 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-A=0x%05x\n", rf_a);
371 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-B=0x%05x\n", rf_b);
394 u8 path, u32 *adc_ic, u32 *adc_qc)
402 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK path(%d)\n", path);
404 base_addr = rtw8822c_get_path_write_addr(path);
405 switch (path) {
419 if (path == RF_PATH_B)
446 dm_info->dack_adck[path] = temp;
467 /* release pull low switch on IQ path */
468 rtw_write_rf(rtwdev, path, 0x8f, BIT(13), 0x1);
471 static void rtw8822c_dac_cal_step1(struct rtw_dev *rtwdev, u8 path)
477 base_addr = rtw8822c_get_path_write_addr(path);
478 read_addr = rtw8822c_get_path_read_addr(path);
480 rtw_write32(rtwdev, base_addr + 0x68, dm_info->dack_adck[path]);
482 if (path == RF_PATH_A) {
517 u8 path, u32 *ic_out, u32 *qc_out)
522 base_addr = rtw8822c_get_path_write_addr(path);
565 static void rtw8822c_dac_cal_step3(struct rtw_dev *rtwdev, u8 path,
575 base_addr = rtw8822c_get_path_write_addr(path);
576 read_addr = rtw8822c_get_path_read_addr(path);
642 static void rtw8822c_dac_cal_step4(struct rtw_dev *rtwdev, u8 path)
644 u32 base_addr = rtw8822c_get_path_write_addr(path);
653 u8 path, u8 vec, u32 w_addr, u32 r_addr)
665 dm_info->dack_msbk[path][vec][i] = val;
669 static void rtw8822c_dac_cal_backup_path(struct rtw_dev *rtwdev, u8 path)
675 if (WARN_ON(path >= 2))
679 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0;
680 r_addr = rtw8822c_get_path_read_addr(path) + 0x10;
681 rtw8822c_dac_cal_backup_vec(rtwdev, path, 0, w_addr, r_addr);
684 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off;
685 r_addr = rtw8822c_get_path_read_addr(path) + 0x10 + r_off;
686 rtw8822c_dac_cal_backup_vec(rtwdev, path, 1, w_addr, r_addr);
724 /* backup path-A I/Q */
729 /* backup path-B I/Q */
843 static bool rtw8822c_dac_cal_restore_path(struct rtw_dev *rtwdev, u8 path)
852 w_i = rtw8822c_get_path_write_addr(path) + 0xb0;
853 r_i = rtw8822c_get_path_read_addr(path) + 0x08;
854 w_q = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off;
855 r_q = rtw8822c_get_path_read_addr(path) + 0x08 + r_off;
862 value = dm_info->dack_msbk[path][0][i];
875 value = dm_info->dack_msbk[path][1][i];
906 /* sample the first element for both path's IQ vector */
960 /* path-A */
976 /* path-B */
1003 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: ic=0x%x, qc=0x%x\n", ic_a, qc_a);
1004 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: ic=0x%x, qc=0x%x\n", ic_b, qc_b);
1005 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: i=0x%x, q=0x%x\n", i_a, q_a);
1006 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: i=0x%x, q=0x%x\n", i_b, q_b);
1031 u8 path;
1033 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1034 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 1);
1035 RF_SET_POWER_TRIM(path, 0x0, 0);
1036 RF_SET_POWER_TRIM(path, 0x1, 1);
1037 RF_SET_POWER_TRIM(path, 0x2, 2);
1038 RF_SET_POWER_TRIM(path, 0x3, 2);
1039 RF_SET_POWER_TRIM(path, 0x4, 3);
1040 RF_SET_POWER_TRIM(path, 0x5, 4);
1041 RF_SET_POWER_TRIM(path, 0x6, 5);
1042 RF_SET_POWER_TRIM(path, 0x7, 6);
1043 RF_SET_POWER_TRIM(path, 0x8, 7);
1044 RF_SET_POWER_TRIM(path, 0x9, 3);
1045 RF_SET_POWER_TRIM(path, 0xa, 4);
1046 RF_SET_POWER_TRIM(path, 0xb, 5);
1047 RF_SET_POWER_TRIM(path, 0xc, 6);
1048 RF_SET_POWER_TRIM(path, 0xd, 7);
1049 RF_SET_POWER_TRIM(path, 0xe, 7);
1050 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 0);
1057 u8 pg_pwr = 0xff, i, path, idx;
1076 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1077 rtw_read8_physical_efuse(rtwdev, rf_efuse_5g[path][i],
1083 bb_gain[path][idx] = FIELD_GET(PPG_5G_MASK, pg_pwr);
1095 u8 pg_therm = 0xff, thermal[2] = {0}, path;
1097 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1098 rtw_read8_physical_efuse(rtwdev, rf_efuse[path], &pg_therm);
1104 thermal[path] = FIELD_GET(GENMASK(3, 1), pg_therm);
1105 thermal[path] |= FIELD_PREP(BIT(3), pg_therm & BIT(0));
1106 rtw_write_rf(rtwdev, path, 0x43, RF_THEMAL_MASK, thermal[path]);
1114 u8 pg_pa_bias = 0xff, path;
1116 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1117 rtw_read8_physical_efuse(rtwdev, rf_efuse_2g[path],
1122 rtw_write_rf(rtwdev, path, RF_PA, RF_PABIAS_2G_MASK, pg_pa_bias);
1124 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1125 rtw_read8_physical_efuse(rtwdev, rf_efuse_5g[path],
1128 rtw_write_rf(rtwdev, path, RF_PA, RF_PABIAS_5G_MASK, pg_pa_bias);
1181 u8 path;
1183 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1184 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path);
1247 static void rtw8822c_txgapk_bb_dpk(struct rtw_dev *rtwdev, u8 path)
1260 if (path == RF_PATH_A) {
1267 } else if (path == RF_PATH_B) {
1279 static void rtw8822c_txgapk_afe_dpk(struct rtw_dev *rtwdev, u8 path)
1285 if (path == RF_PATH_A) {
1287 } else if (path == RF_PATH_B) {
1290 rtw_err(rtwdev, "[TXGAPK] unknown path %d!!\n", path);
1315 static void rtw8822c_txgapk_afe_dpk_restore(struct rtw_dev *rtwdev, u8 path)
1321 if (path == RF_PATH_A) {
1323 } else if (path == RF_PATH_B) {
1326 rtw_err(rtwdev, "[TXGAPK] unknown path %d!!\n", path);
1348 static void rtw8822c_txgapk_bb_dpk_restore(struct rtw_dev *rtwdev, u8 path)
1352 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x0);
1353 rtw_write_rf(rtwdev, path, RF_DIS_BYPASS_TXBB, BIT_TIA_BYPASS, 0x0);
1354 rtw_write_rf(rtwdev, path, RF_DIS_BYPASS_TXBB, BIT_TXBB, 0x0);
1367 if (path == RF_PATH_A) {
1374 } else if (path == RF_PATH_B) {
1398 u8 band, u8 path)
1404 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path);
1427 v = txgapk->rf3f_bp[band][gain][path];
1430 tmp_3f = txgapk->rf3f_bp[band][gain][path];
1435 txgapk->rf3f_bp[band][gain][path]);
1437 tmp_3f = txgapk->rf3f_bp[band][gain][path];
1446 "[TXGAPK] Band=%d 0x1b98[11:0]=0x%03X path=%d\n",
1447 band, tmp_3f, path);
1453 u8 path, band;
1459 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1461 band, path);
1466 static void rtw8822c_txgapk_read_offset(struct rtw_dev *rtwdev, u8 path)
1477 if (path >= ARRAY_SIZE(cfg1_1b00) ||
1478 path >= ARRAY_SIZE(cfg2_1b00) ||
1479 path >= ARRAY_SIZE(set_pi) ||
1480 path >= ARRAY_SIZE(path_setting)) {
1481 rtw_warn(rtwdev, "[TXGAPK] wrong path %d\n", path);
1485 rtw_write32_mask(rtwdev, REG_ANTMAP0, BIT_ANT_PATH, path + 1);
1488 rtw_write32_mask(rtwdev, path_setting[path], MASK20BITS, 0x33312);
1489 rtw_write32_mask(rtwdev, path_setting[path], BIT_PATH_EN, 0x1);
1490 rtw_write32_mask(rtwdev, set_pi[path], BITS_RFC_DIRECT, 0x0);
1491 rtw_write_rf(rtwdev, path, RF_LUTDBG, BIT_TXA_TANK, 0x1);
1492 rtw_write_rf(rtwdev, path, RF_IDAC, BIT_TX_MODE, 0x820);
1493 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path);
1504 rtw_write32_mask(rtwdev, REG_NCTL0, MASKDWORD, cfg1_1b00[path]);
1505 rtw_write32_mask(rtwdev, REG_NCTL0, MASKDWORD, cfg2_1b00[path]);
1511 rtw_write32_mask(rtwdev, set_pi[path], BITS_RFC_DIRECT, 0x2);
1512 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path);
1518 txgapk->offset[0][path] = (s8)FIELD_GET(BIT_GAPK_RPT0, val);
1519 txgapk->offset[1][path] = (s8)FIELD_GET(BIT_GAPK_RPT1, val);
1520 txgapk->offset[2][path] = (s8)FIELD_GET(BIT_GAPK_RPT2, val);
1521 txgapk->offset[3][path] = (s8)FIELD_GET(BIT_GAPK_RPT3, val);
1522 txgapk->offset[4][path] = (s8)FIELD_GET(BIT_GAPK_RPT4, val);
1523 txgapk->offset[5][path] = (s8)FIELD_GET(BIT_GAPK_RPT5, val);
1524 txgapk->offset[6][path] = (s8)FIELD_GET(BIT_GAPK_RPT6, val);
1525 txgapk->offset[7][path] = (s8)FIELD_GET(BIT_GAPK_RPT7, val);
1530 txgapk->offset[8][path] = (s8)FIELD_GET(BIT_GAPK_RPT0, val);
1531 txgapk->offset[9][path] = (s8)FIELD_GET(BIT_GAPK_RPT1, val);
1534 if (txgapk->offset[i][path] & BIT(3))
1535 txgapk->offset[i][path] = txgapk->offset[i][path] |
1539 "[TXGAPK] offset %d %d path=%d\n",
1540 txgapk->offset[i][path], i, path);
1543 static void rtw8822c_txgapk_calculate_offset(struct rtw_dev *rtwdev, u8 path)
1560 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path);
1563 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1);
1564 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x5000f);
1565 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_RF_GAIN, 0x0);
1566 rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x1);
1567 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0f);
1568 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1);
1569 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x1);
1570 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0);
1571 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x1);
1576 rtw8822c_txgapk_read_offset(rtwdev, path);
1582 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path);
1585 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1);
1586 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x50011);
1587 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x3);
1588 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_ATT, 0x3);
1589 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_SW, 0x1);
1590 rtw_write_rf(rtwdev, path,
1592 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0x12);
1593 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1);
1594 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0);
1595 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x1);
1596 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RF_MODE, 0x5);
1610 rtw8822c_txgapk_read_offset(rtwdev, path);
1617 static void rtw8822c_txgapk_rf_restore(struct rtw_dev *rtwdev, u8 path)
1621 if (path >= rtwdev->hal.rf_path_num)
1624 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RF_MODE, 0x3);
1625 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x0);
1626 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x0);
1658 u8 path, band = RF_BAND_2G_OFDM, channel = txgapk->channel;
1679 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1683 v = txgapk->rf3f_bp[band][j][path];
1687 offset_tmp[i] += txgapk->offset[j][path];
1688 txgapk->fianl_offset[i][path] = offset_tmp[i];
1691 v = txgapk->rf3f_bp[band][i][path];
1695 txgapk->rf3f_bp[band][i][path]);
1697 txgapk->rf3f_fs[path][i] = offset_tmp[i];
1704 rtw_write_rf(rtwdev, path, RF_LUTWE2, RFREG_MASK, 0x10000);
1706 rtw_write_rf(rtwdev, path,
1710 txgapk->rf3f_bp[band][i][path],
1712 rtw_write_rf(rtwdev, path, RF_LUTWD0,
1719 rtw_write_rf(rtwdev, path, RF_LUTWE2, RFREG_MASK, 0x0);
1730 u8 path, band, gain, rf0_idx;
1746 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1747 rf18 = rtw_read_rf(rtwdev, path, RF_CFGCH, RFREG_MASK);
1750 three_wire[path], BIT_3WIRE_EN, 0x0);
1751 rtw_write_rf(rtwdev, path,
1753 rtw_write_rf(rtwdev, path,
1755 rtw_write_rf(rtwdev, path,
1757 rtw_write_rf(rtwdev, path,
1761 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC,
1763 v = rtw_read_rf(rtwdev, path,
1765 txgapk->rf3f_bp[band][gain][path] = v & BIT_DATA_L;
1768 "[TXGAPK] 0x5f=0x%03X band=%d path=%d\n",
1769 txgapk->rf3f_bp[band][gain][path],
1770 band, path);
1773 rtw_write_rf(rtwdev, path, RF_CFGCH, RFREG_MASK, rf18);
1775 three_wire[path], BIT_3WIRE_EN, 0x3);
1787 u8 path;
1809 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1810 txgapk->channel = rtw_read_rf(rtwdev, path,
1812 rtw8822c_txgapk_bb_dpk(rtwdev, path);
1813 rtw8822c_txgapk_afe_dpk(rtwdev, path);
1814 rtw8822c_txgapk_calculate_offset(rtwdev, path);
1815 rtw8822c_txgapk_rf_restore(rtwdev, path);
1816 rtw8822c_txgapk_afe_dpk_restore(rtwdev, path);
1817 rtw8822c_txgapk_bb_dpk_restore(rtwdev, path);
1849 u8 path;
1851 for (path = RF_PATH_A; path < RTW_RF_PATH_MAX; path++) {
1852 dm_info->delta_power_index[path] = 0;
1853 ewma_thermal_init(&dm_info->avg_thermal[path]);
1854 dm_info->thermal_avg[path] = 0xff;
2557 int path;
2585 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) {
2586 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1);
2587 dm_info->rssi[path] = rssi;
2606 int path;
2643 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) {
2644 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1);
2645 dm_info->rssi[path] = rssi;
2646 if (path == RF_PATH_A) {
2649 } else if (path == RF_PATH_B) {
2653 dm_info->rx_snr[path] = pkt_stat->rx_snr[path] >> 1;
2654 dm_info->cfo_tail[path] = (pkt_stat->cfo_tail[path] * 5) >> 1;
2656 rx_evm = pkt_stat->rx_evm[path];
2664 dm_info->rx_evm_dbm[path] = evm_dbm;
2738 u8 path;
2740 for (path = 0; path < hal->rf_path_num; path++) {
2742 rtw_write32_mask(rtwdev, txref_cck[path], 0x7f0000,
2743 tx_pwr_ref_cck[path]);
2745 for (path = 0; path < hal->rf_path_num; path++) {
2747 rtw_write32_mask(rtwdev, txref_ofdm[path], 0x1fc00,
2748 tx_pwr_ref_ofdm[path]);
2819 rtw_warn(rtwdev, "unsupported tx path 0x%x\n", antenna_tx);
2823 /* path B only is not available for RX */
2829 rtw_warn(rtwdev, "unsupported rx path 0x%x\n", antenna_rx);
3037 * or antenna path is separated
3288 static void rtw8822c_dpk_rxbb_dc_cal(struct rtw_dev *rtwdev, u8 path)
3290 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800);
3292 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84801);
3294 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800);
3297 static u8 rtw8822c_dpk_dc_corr_check(struct rtw_dev *rtwdev, u8 path)
3354 u8 path;
3356 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
3357 rtw_write_rf(rtwdev, path, RF_RXAGC_OFFSET, RFREG_MASK, 0x0);
3358 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1));
3371 static u32 rtw8822c_dpk_rf_setting(struct rtw_dev *rtwdev, u8 path)
3375 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x50017);
3376 ori_txbb = rtw_read_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK);
3378 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1);
3379 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_PWR_TRIM, 0x1);
3380 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_BB_GAIN, 0x0);
3381 rtw_write_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK, ori_txbb);
3384 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_RF_GAIN, 0x1);
3385 rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x0);
3387 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x0);
3388 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_ATT, 0x6);
3389 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_SW, 0x1);
3390 rtw_write_rf(rtwdev, path, RF_RXA_MIX_GAIN, BIT_RXA_MIX_GAIN, 0);
3393 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf);
3394 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1);
3395 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0);
3398 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x2);
3400 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x1);
3402 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT(1), 0x1);
3409 static u16 rtw8822c_dpk_get_cmd(struct rtw_dev *rtwdev, u8 action, u8 path)
3416 cmd = 0x14 + path;
3419 cmd = 0x16 + path + bw;
3422 cmd = 0x1a + path;
3425 cmd = 0x1c + path + bw;
3434 static u8 rtw8822c_dpk_one_shot(struct rtw_dev *rtwdev, u8 path, u8 action)
3452 0x8 | (path << 1));
3455 dpk_cmd = rtw8822c_dpk_get_cmd(rtwdev, action, path);
3464 0x8 | (path << 1));
3475 static u16 rtw8822c_dpk_dgain_read(struct rtw_dev *rtwdev, u8 path)
3487 static u8 rtw8822c_dpk_thermal_read(struct rtw_dev *rtwdev, u8 path)
3489 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1);
3490 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x0);
3491 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1);
3494 return (u8)rtw_read_rf(rtwdev, path, RF_T_METER, 0x0007e);
3497 static u32 rtw8822c_dpk_pas_read(struct rtw_dev *rtwdev, u8 path)
3501 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1));
3546 static u8 rtw8822c_dpk_gainloss_result(struct rtw_dev *rtwdev, u8 path)
3550 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3561 static u8 rtw8822c_dpk_agc_gain_chk(struct rtw_dev *rtwdev, u8 path,
3567 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC);
3568 dgain = rtw8822c_dpk_dgain_read(rtwdev, path);
3578 static u8 rtw8822c_dpk_agc_loss_chk(struct rtw_dev *rtwdev, u8 path)
3582 loss = rtw8822c_dpk_pas_read(rtwdev, path);
3602 u8 path;
3610 data->txbb = (u8)rtw_read_rf(rtwdev, data->path, RF_TX_GAIN,
3612 data->pga = (u8)rtw_read_rf(rtwdev, data->path, RF_MODE_TRXAGC,
3620 state = rtw8822c_dpk_agc_gain_chk(rtwdev, data->path,
3641 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc);
3643 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0);
3656 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc);
3658 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf);
3678 rtw_write_rf(rtwdev, data->path, RF_TX_GAIN, BIT_GAIN_TXBB, data->txbb);
3699 u8 path = data->path;
3702 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_GAIN_LOSS);
3703 state = rtw8822c_dpk_agc_loss_chk(rtwdev, path);
3714 static u8 rtw8822c_dpk_pas_agc(struct rtw_dev *rtwdev, u8 path,
3723 data.path = path;
3769 static void rtw8822c_dpk_coef_tbl_apply(struct rtw_dev *rtwdev, u8 path)
3777 dpk_info->coef[path][i] = rtw8822c_dpk_coef_transfer(rtwdev);
3781 static void rtw8822c_dpk_get_coef(struct rtw_dev *rtwdev, u8 path)
3785 if (path == RF_PATH_A) {
3788 } else if (path == RF_PATH_B) {
3793 rtw8822c_dpk_coef_tbl_apply(rtwdev, path);
3796 static u8 rtw8822c_dpk_coef_read(struct rtw_dev *rtwdev, u8 path)
3803 coef_i = FIELD_GET(0x1fff0000, dpk_info->coef[path][addr]);
3804 coef_q = FIELD_GET(0x1fff, dpk_info->coef[path][addr]);
3814 static void rtw8822c_dpk_coef_write(struct rtw_dev *rtwdev, u8 path, u8 result)
3831 coef = dpk_info->coef[path][addr];
3833 rtw_write32(rtwdev, reg[path] + addr * 4, coef);
3838 u8 path, u8 result)
3842 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3849 dpk_info->result[path] = result;
3850 dpk_info->dpk_txagc[path] = rtw_read8(rtwdev, REG_DPD_AGC);
3852 rtw8822c_dpk_coef_write(rtwdev, path, result);
3855 static u32 rtw8822c_dpk_gainloss(struct rtw_dev *rtwdev, u8 path)
3860 ori_txbb = rtw8822c_dpk_rf_setting(rtwdev, path);
3861 ori_txagc = (u8)rtw_read_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_TXAGC);
3863 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path);
3864 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC);
3865 rtw8822c_dpk_dgain_read(rtwdev, path);
3867 if (rtw8822c_dpk_dc_corr_check(rtwdev, path)) {
3868 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path);
3869 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC);
3870 rtw8822c_dpk_dc_corr_check(rtwdev, path);
3873 t1 = rtw8822c_dpk_thermal_read(rtwdev, path);
3874 tx_bb = rtw8822c_dpk_pas_agc(rtwdev, path, false, true);
3875 tx_agc_search = rtw8822c_dpk_gainloss_result(rtwdev, path);
3882 rtw_write_rf(rtwdev, path, RF_TX_GAIN, BIT_GAIN_TXBB, tx_bb);
3886 t2 = rtw8822c_dpk_thermal_read(rtwdev, path);
3888 dpk_info->thermal_dpk_delta[path] = abs(t2 - t1);
3893 static u8 rtw8822c_dpk_by_path(struct rtw_dev *rtwdev, u32 tx_agc, u8 path)
3897 result = rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DO_DPK);
3899 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3903 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x33e14);
3905 rtw8822c_dpk_get_coef(rtwdev, path);
3910 static void rtw8822c_dpk_cal_gs(struct rtw_dev *rtwdev, u8 path)
3915 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3923 if (path == RF_PATH_A) {
3940 0x05020000 | (BIT(path) << 28));
3948 0x05020008 | (BIT(path) << 28));
3951 rtw_write32_mask(rtwdev, REG_DPD_CTL0, MASKBYTE3, 0x8 | path);
3953 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_CAL_PWR);
3956 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3961 if (path == RF_PATH_A)
3972 if (path == RF_PATH_A)
3977 dpk_info->dpk_gs[path] = tmp_gs;
3985 u8 path;
3997 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
3998 i_scaling = 0x16c00 / dpk_info->dpk_gs[path];
4000 rtw_write32_mask(rtwdev, 0x1b18 + offset[path], MASKHWORD,
4002 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path],
4004 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path],
4006 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path],
4008 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0 + offset[path],
4013 static void rtw8822c_dpk_on(struct rtw_dev *rtwdev, u8 path)
4017 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DPK_ON);
4019 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
4022 if (test_bit(path, dpk_info->dpk_path_ok))
4023 rtw8822c_dpk_cal_gs(rtwdev, path);
4027 u32 dpk_txagc, u8 path)
4032 if (rtw8822c_dpk_coef_read(rtwdev, path))
4040 rtw8822c_dpk_fill_result(rtwdev, dpk_txagc, path, result);
4048 u8 path;
4050 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
4051 clear_bit(path, dpk_info->dpk_path_ok);
4053 0x8 | (path << 1));
4056 dpk_info->dpk_txagc[path] = 0;
4057 dpk_info->result[path] = 0;
4058 dpk_info->dpk_gs[path] = 0x5b;
4059 dpk_info->pre_pwsf[path] = 0;
4060 dpk_info->thermal_dpk[path] = rtw8822c_dpk_thermal_read(rtwdev,
4061 path);
4065 static void rtw8822c_dpk_calibrate(struct rtw_dev *rtwdev, u8 path)
4071 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] s%d dpk start\n", path);
4073 dpk_txagc = rtw8822c_dpk_gainloss(rtwdev, path);
4075 dpk_fail = rtw8822c_dpk_by_path(rtwdev, dpk_txagc, path);
4077 if (!rtw8822c_dpk_check_pass(rtwdev, dpk_fail, dpk_txagc, path))
4080 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] s%d dpk finish\n", path);
4082 if (dpk_info->result[path])
4083 set_bit(path, dpk_info->dpk_path_ok);
4120 u8 path;
4127 for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
4129 0x8 | (path << 1));
4135 rtw_write8(rtwdev, REG_DPD_AGC, dpk_info->dpk_txagc[path]);
4137 rtw8822c_dpk_coef_write(rtwdev, path,
4138 test_bit(path, dpk_info->dpk_path_ok));
4140 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DPK_ON);
4144 if (path == RF_PATH_A)
4146 dpk_info->dpk_gs[path]);
4149 dpk_info->dpk_gs[path]);
4184 u8 path;
4193 for (path = RF_PATH_A; path < DPK_RF_PATH_NUM; path++)
4194 ewma_thermal_init(&dpk_info->avg_thermal[path]);
4210 for (path = 0; path < rtwdev->hal.rf_path_num; path++)
4211 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path);
4227 u8 path;
4234 for (path = 0; path < DPK_RF_PATH_NUM; path++) {
4235 thermal_value[path] = rtw8822c_dpk_thermal_read(rtwdev, path);
4236 ewma_thermal_add(&dpk_info->avg_thermal[path],
4237 thermal_value[path]);
4238 thermal_value[path] =
4239 ewma_thermal_read(&dpk_info->avg_thermal[path]);
4240 delta_dpk[path] = dpk_info->thermal_dpk[path] -
4241 thermal_value[path];
4242 offset[path] = delta_dpk[path] -
4243 dpk_info->thermal_dpk_delta[path];
4244 offset[path] &= 0x7f;
4246 if (offset[path] != dpk_info->pre_pwsf[path]) {
4248 0x8 | (path << 1));
4250 offset[path]);
4251 dpk_info->pre_pwsf[path] = offset[path];
4480 static void rtw8822c_pwr_track_stats(struct rtw_dev *rtwdev, u8 path)
4484 if (rtwdev->efuse.thermal_meter[path] == 0xff)
4487 thermal_value = rtw_read_rf(rtwdev, path, RF_T_METER, 0x7e);
4488 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, path);
4493 u8 path)
4498 delta = rtw_phy_pwrtrack_get_delta(rtwdev, path);
4499 dm_info->delta_power_index[path] =
4500 rtw_phy_pwrtrack_get_pwridx(rtwdev, swing_table, path, path,
4502 rtw8822c_pwrtrack_set(rtwdev, path);