Lines Matching defs:val
112 u32 val;
123 backup[i].val = rtw_read32(rtwdev, addrs[i]);
129 val = rtw_read_rf(rtwdev, path, reg, RFREG_MASK);
131 backup_rf[path * i + i].val = val;
141 u32 val;
148 val = backup_rf[path * i + i].val;
150 rtw_write_rf(rtwdev, path, reg, RFREG_MASK, val);
209 static void rtw8822c_dac_iq_offset(struct rtw_dev *rtwdev, u32 *vec, u32 *val)
232 *val = t;
656 u16 val;
664 val = (u16)rtw_read32_mask(rtwdev, r_addr, 0x7fc0000);
665 dm_info->dack_msbk[path][vec][i] = val;
692 u8 val;
694 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000);
695 dm_info->dack_dck[RF_PATH_A][0][0] = val;
696 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_1, 0xf);
697 dm_info->dack_dck[RF_PATH_A][0][1] = val;
698 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000);
699 dm_info->dack_dck[RF_PATH_A][1][0] = val;
700 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_1, 0xf);
701 dm_info->dack_dck[RF_PATH_A][1][1] = val;
703 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000);
704 dm_info->dack_dck[RF_PATH_B][0][0] = val;
705 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_1, 0xf);
706 dm_info->dack_dck[RF_PATH_B][1][0] = val;
707 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000);
708 dm_info->dack_dck[RF_PATH_B][0][1] = val;
709 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_1, 0xf);
710 dm_info->dack_dck[RF_PATH_B][1][1] = val;
746 u8 val;
749 val = dm_info->dack_dck[RF_PATH_A][0][0];
750 rtw_write32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000, val);
751 val = dm_info->dack_dck[RF_PATH_A][0][1];
752 rtw_write32_mask(rtwdev, REG_DCKA_I_1, 0xf, val);
755 val = dm_info->dack_dck[RF_PATH_A][1][0];
756 rtw_write32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000, val);
757 val = dm_info->dack_dck[RF_PATH_A][1][1];
758 rtw_write32_mask(rtwdev, REG_DCKA_Q_1, 0xf, val);
761 val = dm_info->dack_dck[RF_PATH_B][0][0];
762 rtw_write32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000, val);
763 val = dm_info->dack_dck[RF_PATH_B][0][1];
764 rtw_write32_mask(rtwdev, REG_DCKB_I_1, 0xf, val);
767 val = dm_info->dack_dck[RF_PATH_B][1][0];
768 rtw_write32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000, val);
769 val = dm_info->dack_dck[RF_PATH_B][1][1];
770 rtw_write32_mask(rtwdev, REG_DCKB_Q_1, 0xf, val);
1474 u32 val;
1507 read_poll_timeout(rtw_read32_mask, val,
1508 val == 0x55, 1000, 100000, false,
1516 val = rtw_read32(rtwdev, REG_STAT_RPT);
1518 txgapk->offset[0][path] = (s8)FIELD_GET(BIT_GAPK_RPT0, val);
1519 txgapk->offset[1][path] = (s8)FIELD_GET(BIT_GAPK_RPT1, val);
1520 txgapk->offset[2][path] = (s8)FIELD_GET(BIT_GAPK_RPT2, val);
1521 txgapk->offset[3][path] = (s8)FIELD_GET(BIT_GAPK_RPT3, val);
1522 txgapk->offset[4][path] = (s8)FIELD_GET(BIT_GAPK_RPT4, val);
1523 txgapk->offset[5][path] = (s8)FIELD_GET(BIT_GAPK_RPT5, val);
1524 txgapk->offset[6][path] = (s8)FIELD_GET(BIT_GAPK_RPT6, val);
1525 txgapk->offset[7][path] = (s8)FIELD_GET(BIT_GAPK_RPT7, val);
1528 val = rtw_read32(rtwdev, REG_STAT_RPT);
1530 txgapk->offset[8][path] = (s8)FIELD_GET(BIT_GAPK_RPT0, val);
1531 txgapk->offset[9][path] = (s8)FIELD_GET(BIT_GAPK_RPT1, val);
2922 u32 val;
2929 read_poll_timeout(rtw_read_rf, val, val != 0x1, 1000, 100000,
3242 bckp[i].val = rtw_read32(rtwdev, reg[i]);
3520 static u32 rtw8822c_psd_log2base(u32 val)
3528 if (val == 0)
3531 val_integerd_b = __fls(val) + 1;
3533 tmp = (val * 100) / (1 << val_integerd_b);
4256 #define XCAP_EXTEND(val) ({typeof(val) _v = (val); _v | _v << 7; })
4261 u32 val = 0;
4263 val = XCAP_EXTEND(crystal_cap);
4265 rtw_write32_mask(rtwdev, REG_ANAPAR_XTAL_0, BIT_XCAP_0, val);
4301 #define REPORT_TO_KHZ(val) ({typeof(val) _v = (val); (_v << 1) + (_v >> 1); })