Lines Matching refs:addr
16 u32 addr;
129 edcca_th[EDCCA_TH_L2H_IDX].hw_reg.addr,
133 edcca_th[EDCCA_TH_H2L_IDX].hw_reg.addr,
204 u32 addr, mask;
215 addr = chip->dig[0].addr;
217 dm_info->igi_history[0] = rtw_read32_mask(rtwdev, addr, mask);
231 u32 addr, mask;
236 rtw_write32_mask(rtwdev, dig_cck->addr, dig_cck->mask, igi >> 1);
240 addr = chip->dig[path].addr;
242 rtw_write32_mask(rtwdev, addr, mask, igi);
895 u32 addr, u32 mask)
907 addr &= 0xff;
908 direct_addr = base_addr[rf_path] + (addr << 2);
918 u32 addr, u32 mask)
942 addr &= 0xff;
945 val32 = (val32 & ~LSSI_READ_ADDR_MASK) | (addr << 23);
967 u32 addr, u32 mask, u32 data)
981 addr &= 0xff;
985 old_data = chip->ops->read_rf(rtwdev, rf_path, addr, RFREG_MASK);
996 data_and_addr = ((addr << 20) | (data & 0x000fffff)) & 0x0fffffff;
1007 u32 addr, u32 mask, u32 data)
1019 addr &= 0xff;
1020 direct_addr = base_addr[rf_path] + (addr << 2);
1031 u32 addr, u32 mask, u32 data)
1033 if (addr != 0x00)
1034 return rtw_phy_write_rf_reg(rtwdev, rf_path, addr, mask, data);
1036 return rtw_phy_write_rf_reg_sipi(rtwdev, rf_path, addr, mask, data);
1127 (*tbl->do_cfg)(rtwdev, tbl, p->cfg.addr, p->cfg.data);
1145 u32 addr, u32 mask, u32 val, u8 *rate,
1150 switch (addr) {
1443 rtw_warn(rtwdev, "invalid tx power index addr 0x%08x\n", addr);
1486 if (p->addr == 0xfe || p->addr == 0xffe) {
1491 p->tx_num, p->addr, p->bitmask,
1696 u32 addr, u32 data)
1698 rtw_write8(rtwdev, addr, data);
1703 u32 addr, u32 data)
1705 rtw_write32(rtwdev, addr, data);
1710 u32 addr, u32 data)
1712 if (addr == 0xfe)
1714 else if (addr == 0xfd)
1716 else if (addr == 0xfc)
1718 else if (addr == 0xfb)
1720 else if (addr == 0xfa)
1722 else if (addr == 0xf9)
1725 rtw_write32(rtwdev, addr, data);
1730 u32 addr, u32 data)
1732 if (addr == 0xffe) {
1734 } else if (addr == 0xfe) {
1737 rtw_write_rf(rtwdev, tbl->rf_path, addr, RFREG_MASK, data);