Lines Matching refs:rtwdev
12 void rtw_set_channel_mac(struct rtw_dev *rtwdev, u8 channel, u8 bw,
26 rtw_write8(rtwdev, REG_DATA_SC,
29 value32 = rtw_read32(rtwdev, REG_WMAC_TRXPTCL_CTL);
42 rtw_write32(rtwdev, REG_WMAC_TRXPTCL_CTL, value32);
44 if (rtw_chip_wcpu_11n(rtwdev))
47 value32 = rtw_read32(rtwdev, REG_AFE_CTRL1) & ~(BIT_MAC_CLK_SEL);
49 rtw_write32(rtwdev, REG_AFE_CTRL1, value32);
51 rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED);
52 rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED);
54 value8 = rtw_read8(rtwdev, REG_CCK_CHECK);
58 rtw_write8(rtwdev, REG_CCK_CHECK, value8);
62 static int rtw_mac_pre_system_cfg(struct rtw_dev *rtwdev)
68 rtw_write8(rtwdev, REG_RSV_CTRL, 0);
70 if (rtw_chip_wcpu_11n(rtwdev)) {
71 if (rtw_read32(rtwdev, REG_SYS_CFG1) & BIT_LDO)
72 rtw_write8(rtwdev, REG_LDO_SWR_CTRL, LDO_SEL);
74 rtw_write8(rtwdev, REG_LDO_SWR_CTRL, SPS_SEL);
78 switch (rtw_hci_type(rtwdev)) {
80 rtw_write32_set(rtwdev, REG_HCI_OPT_CTRL, BIT_USB_SUS_DIS);
83 rtw_write8_clr(rtwdev, REG_SDIO_HSUS_CTRL, BIT_HCI_SUS_REQ);
86 if (rtw_read8(rtwdev, REG_SDIO_HSUS_CTRL) & BIT_HCI_RESUME_RDY)
93 rtw_err(rtwdev, "failed to poll REG_SDIO_HSUS_CTRL[1]");
97 if (rtw_sdio_is_sdio30_supported(rtwdev))
98 rtw_write8_set(rtwdev, REG_HCI_OPT_CTRL + 2,
101 rtw_write8_clr(rtwdev, REG_HCI_OPT_CTRL + 2,
111 value32 = rtw_read32(rtwdev, REG_PAD_CTRL1);
113 rtw_write32(rtwdev, REG_PAD_CTRL1, value32);
115 value32 = rtw_read32(rtwdev, REG_LED_CFG);
117 rtw_write32(rtwdev, REG_LED_CFG, value32);
119 value32 = rtw_read32(rtwdev, REG_GPIO_MUXCFG);
121 rtw_write32(rtwdev, REG_GPIO_MUXCFG, value32);
124 value8 = rtw_read8(rtwdev, REG_SYS_FUNC_EN);
126 rtw_write8(rtwdev, REG_SYS_FUNC_EN, value8);
128 value8 = rtw_read8(rtwdev, REG_RF_CTRL);
130 rtw_write8(rtwdev, REG_RF_CTRL, value8);
132 value32 = rtw_read32(rtwdev, REG_WLRF1);
134 rtw_write32(rtwdev, REG_WLRF1, value32);
139 static bool do_pwr_poll_cmd(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target)
147 rtwdev, addr) == 0;
150 static int rtw_pwr_cmd_polling(struct rtw_dev *rtwdev,
161 if (do_pwr_poll_cmd(rtwdev, offset, cmd->mask, cmd->value))
164 if (rtw_hci_type(rtwdev) != RTW_HCI_TYPE_PCIE)
168 value = rtw_read8(rtwdev, REG_SYS_PW_CTRL);
169 if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D)
170 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value & ~BIT_PFM_WOWL);
171 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value | BIT_PFM_WOWL);
172 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value & ~BIT_PFM_WOWL);
173 if (rtwdev->chip->id == RTW_CHIP_TYPE_8723D)
174 rtw_write8(rtwdev, REG_SYS_PW_CTRL, value | BIT_PFM_WOWL);
176 if (do_pwr_poll_cmd(rtwdev, offset, cmd->mask, cmd->value))
180 rtw_err(rtwdev, "failed to poll offset=0x%x mask=0x%x value=0x%x\n",
185 static int rtw_sub_pwr_seq_parser(struct rtw_dev *rtwdev, u8 intf_mask,
205 value = rtw_read8(rtwdev, offset);
208 rtw_write8(rtwdev, offset, value);
211 if (rtw_pwr_cmd_polling(rtwdev, cur_cmd))
230 static int rtw_pwr_seq_parser(struct rtw_dev *rtwdev,
240 cut = rtwdev->hal.cut_version;
242 switch (rtw_hci_type(rtwdev)) {
261 ret = rtw_sub_pwr_seq_parser(rtwdev, intf_mask, cut_mask, cmd);
271 static int rtw_mac_power_switch(struct rtw_dev *rtwdev, bool pwr_on)
273 const struct rtw_chip_info *chip = rtwdev->chip;
280 if (rtw_chip_wcpu_11ac(rtwdev)) {
281 rpwm = rtw_read8(rtwdev, rtwdev->hci.rpwm_addr);
284 if (rtw_read16(rtwdev, REG_MCUFW_CTRL) == 0xC078) {
286 rtw_write8(rtwdev, rtwdev->hci.rpwm_addr, rpwm);
290 if (rtw_read8(rtwdev, REG_CR) == 0xea)
292 else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB &&
293 (rtw_read8(rtwdev, REG_SYS_STATUS1 + 1) & BIT(0)))
301 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO) {
302 imr = rtw_read32(rtwdev, REG_SDIO_HIMR);
303 rtw_write32(rtwdev, REG_SDIO_HIMR, 0);
307 clear_bit(RTW_FLAG_POWERON, rtwdev->flags);
310 ret = rtw_pwr_seq_parser(rtwdev, pwr_seq);
312 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO)
313 rtw_write32(rtwdev, REG_SDIO_HIMR, imr);
316 set_bit(RTW_FLAG_POWERON, rtwdev->flags);
321 static int __rtw_mac_init_system_cfg(struct rtw_dev *rtwdev)
323 u8 sys_func_en = rtwdev->chip->sys_func_en;
327 value = rtw_read32(rtwdev, REG_CPU_DMEM_CON);
329 rtw_write32(rtwdev, REG_CPU_DMEM_CON, value);
331 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, sys_func_en);
332 value8 = (rtw_read8(rtwdev, REG_CR_EXT + 3) & 0xF0) | 0x0C;
333 rtw_write8(rtwdev, REG_CR_EXT + 3, value8);
336 tmp = rtw_read32(rtwdev, REG_MCUFW_CTRL);
338 rtw_write32(rtwdev, REG_MCUFW_CTRL, tmp & (~BIT_BOOT_FSPI_EN));
339 value = rtw_read32(rtwdev, REG_GPIO_MUXCFG) & (~BIT_FSPI_EN);
340 rtw_write32(rtwdev, REG_GPIO_MUXCFG, value);
346 static int __rtw_mac_init_system_cfg_legacy(struct rtw_dev *rtwdev)
348 rtw_write8(rtwdev, REG_CR, 0xff);
350 rtw_write8(rtwdev, REG_HWSEQ_CTRL, 0x7f);
353 rtw_write8_set(rtwdev, REG_SYS_CLKR, BIT_WAKEPAD_EN);
354 rtw_write16_clr(rtwdev, REG_GPIO_MUXCFG, BIT_EN_SIC);
356 rtw_write16(rtwdev, REG_CR, 0x2ff);
361 static int rtw_mac_init_system_cfg(struct rtw_dev *rtwdev)
363 if (rtw_chip_wcpu_11n(rtwdev))
364 return __rtw_mac_init_system_cfg_legacy(rtwdev);
366 return __rtw_mac_init_system_cfg(rtwdev);
369 int rtw_mac_power_on(struct rtw_dev *rtwdev)
373 ret = rtw_mac_pre_system_cfg(rtwdev);
377 ret = rtw_mac_power_switch(rtwdev, true);
379 rtw_mac_power_switch(rtwdev, false);
381 ret = rtw_mac_pre_system_cfg(rtwdev);
385 ret = rtw_mac_power_switch(rtwdev, true);
392 ret = rtw_mac_init_system_cfg(rtwdev);
399 rtw_err(rtwdev, "mac power on failed");
403 void rtw_mac_power_off(struct rtw_dev *rtwdev)
405 rtw_mac_power_switch(rtwdev, false);
431 static void wlan_cpu_enable(struct rtw_dev *rtwdev, bool enable)
435 rtw_write8_set(rtwdev, REG_RSV_CTRL + 1, BIT_WLMCU_IOIF);
438 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN);
441 rtw_write8_clr(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN);
444 rtw_write8_clr(rtwdev, REG_RSV_CTRL + 1, BIT_WLMCU_IOIF);
450 static void download_firmware_reg_backup(struct rtw_dev *rtwdev,
459 bckp[bckp_idx].val = rtw_read8(rtwdev, REG_TXDMA_PQ_MAP + 1);
462 rtw_write8(rtwdev, REG_TXDMA_PQ_MAP + 1, tmp);
467 bckp[bckp_idx].val = rtw_read8(rtwdev, REG_CR);
474 rtw_write8(rtwdev, REG_CR, tmp);
475 rtw_write32(rtwdev, REG_H2CQ_CSR, BIT_H2CQ_FULL);
480 bckp[bckp_idx].val = rtw_read16(rtwdev, REG_FIFOPAGE_INFO_1);
484 bckp[bckp_idx].val = rtw_read32(rtwdev, REG_RQPN_CTRL_2) | BIT_LD_RQPN;
486 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, 0x200);
487 rtw_write32(rtwdev, REG_RQPN_CTRL_2, bckp[bckp_idx - 1].val);
489 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO)
490 rtw_read32(rtwdev, REG_SDIO_FREE_TXPG);
493 tmp = rtw_read8(rtwdev, REG_BCN_CTRL);
499 rtw_write8(rtwdev, REG_BCN_CTRL, tmp);
504 static void download_firmware_reset_platform(struct rtw_dev *rtwdev)
506 rtw_write8_clr(rtwdev, REG_CPU_DMEM_CON + 2, BIT_WL_PLATFORM_RST >> 16);
507 rtw_write8_clr(rtwdev, REG_SYS_CLK_CTRL + 1, BIT_CPU_CLK_EN >> 8);
508 rtw_write8_set(rtwdev, REG_CPU_DMEM_CON + 2, BIT_WL_PLATFORM_RST >> 16);
509 rtw_write8_set(rtwdev, REG_SYS_CLK_CTRL + 1, BIT_CPU_CLK_EN >> 8);
512 static void download_firmware_reg_restore(struct rtw_dev *rtwdev,
516 rtw_restore_reg(rtwdev, bckp, bckp_num);
521 static int send_firmware_pkt_rsvd_page(struct rtw_dev *rtwdev, u16 pg_addr,
531 ret = rtw_fw_write_data_rsvd_page(rtwdev, pg_addr, buf, size);
537 send_firmware_pkt(struct rtw_dev *rtwdev, u16 pg_addr, const u8 *data, u32 size)
541 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB &&
545 ret = send_firmware_pkt_rsvd_page(rtwdev, pg_addr, data, size);
547 rtw_err(rtwdev, "failed to download rsvd page\n");
553 iddma_enable(struct rtw_dev *rtwdev, u32 src, u32 dst, u32 ctrl)
555 rtw_write32(rtwdev, REG_DDMA_CH0SA, src);
556 rtw_write32(rtwdev, REG_DDMA_CH0DA, dst);
557 rtw_write32(rtwdev, REG_DDMA_CH0CTRL, ctrl);
559 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0))
565 static int iddma_download_firmware(struct rtw_dev *rtwdev, u32 src, u32 dst,
570 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0))
577 if (iddma_enable(rtwdev, src, dst, ch0_ctrl))
583 int rtw_ddma_to_fw_fifo(struct rtw_dev *rtwdev, u32 ocp_src, u32 size)
587 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0)) {
588 rtw_dbg(rtwdev, RTW_DBG_FW, "busy to start ddma\n");
594 if (iddma_enable(rtwdev, ocp_src, OCPBASE_RXBUF_FW_88XX, ch0_ctrl)) {
595 rtw_dbg(rtwdev, RTW_DBG_FW, "busy to complete ddma\n");
603 check_fw_checksum(struct rtw_dev *rtwdev, u32 addr)
607 fw_ctrl = rtw_read8(rtwdev, REG_MCUFW_CTRL);
609 if (rtw_read32(rtwdev, REG_DDMA_CH0CTRL) & BIT_DDMACH0_CHKSUM_STS) {
613 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
617 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
620 rtw_err(rtwdev, "invalid fw checksum\n");
627 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
630 rtw_write8(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
637 download_firmware_to_mem(struct rtw_dev *rtwdev, const u8 *data,
640 const struct rtw_chip_info *chip = rtwdev->chip;
654 val = rtw_read32(rtwdev, REG_DDMA_CH0CTRL);
656 rtw_write32(rtwdev, REG_DDMA_CH0CTRL, val);
664 ret = send_firmware_pkt(rtwdev, (u16)(src >> 7),
669 ret = iddma_download_firmware(rtwdev, OCPBASE_TXBUF_88XX +
681 if (!check_fw_checksum(rtwdev, dst))
688 start_download_firmware(struct rtw_dev *rtwdev, const u8 *data, u32 size)
707 val = (u16)(rtw_read16(rtwdev, REG_MCUFW_CTRL) & 0x3800);
709 rtw_write16(rtwdev, REG_MCUFW_CTRL, val);
714 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, dmem_size);
721 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr, imem_size);
729 ret = download_firmware_to_mem(rtwdev, cur_fw, 0, addr,
738 static int download_firmware_validate(struct rtw_dev *rtwdev)
742 if (!check_hw_ready(rtwdev, REG_MCUFW_CTRL, FW_READY_MASK, FW_READY)) {
743 fw_key = rtw_read32(rtwdev, REG_FW_DBG7) & FW_KEY_MASK;
745 rtw_err(rtwdev, "invalid fw key\n");
752 static void download_firmware_end_flow(struct rtw_dev *rtwdev)
756 rtw_write32(rtwdev, REG_TXDMA_STATUS, BTI_PAGE_OVF);
759 fw_ctrl = rtw_read16(rtwdev, REG_MCUFW_CTRL);
764 rtw_write16(rtwdev, REG_MCUFW_CTRL, fw_ctrl);
767 static int __rtw_download_firmware(struct rtw_dev *rtwdev,
779 if (!ltecoex_read_reg(rtwdev, 0x38, <ecoex_bckp))
782 wlan_cpu_enable(rtwdev, false);
784 download_firmware_reg_backup(rtwdev, bckp);
785 download_firmware_reset_platform(rtwdev);
787 ret = start_download_firmware(rtwdev, data, size);
791 download_firmware_reg_restore(rtwdev, bckp, DLFW_RESTORE_REG_NUM);
793 download_firmware_end_flow(rtwdev);
795 wlan_cpu_enable(rtwdev, true);
797 if (!ltecoex_reg_write(rtwdev, 0x38, ltecoex_bckp)) {
802 ret = download_firmware_validate(rtwdev);
807 rtw_hci_setup(rtwdev);
809 rtwdev->h2c.last_box_num = 0;
810 rtwdev->h2c.seq = 0;
812 set_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags);
818 rtw_write8_clr(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN);
819 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, BIT_FEN_CPUEN);
824 static void en_download_firmware_legacy(struct rtw_dev *rtwdev, bool en)
829 wlan_cpu_enable(rtwdev, false);
830 wlan_cpu_enable(rtwdev, true);
832 rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN);
835 if (rtw_read8(rtwdev, REG_MCUFW_CTRL) & BIT_MCUFWDL_EN)
837 rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN);
840 rtw_err(rtwdev, "failed to check fw download ready\n");
842 rtw_write32_clr(rtwdev, REG_MCUFW_CTRL, BIT_ROM_DLEN);
844 rtw_write8_clr(rtwdev, REG_MCUFW_CTRL, BIT_MCUFWDL_EN);
849 write_firmware_page(struct rtw_dev *rtwdev, u32 page, const u8 *data, u32 size)
862 val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL);
865 rtw_write32(rtwdev, REG_MCUFW_CTRL, val32);
868 rtw_write32(rtwdev, write_addr, le32_to_cpu(*ptr));
876 rtw_write32(rtwdev, write_addr, le32_to_cpu(remain_data));
881 download_firmware_legacy(struct rtw_dev *rtwdev, const u8 *data, u32 size)
893 rtw_write8_set(rtwdev, REG_MCUFW_CTRL, BIT_FWDL_CHK_RPT);
896 write_firmware_page(rtwdev, page, data, DLFW_PAGE_SIZE_LEGACY);
900 write_firmware_page(rtwdev, page, data, last_page_size);
902 if (!check_hw_ready(rtwdev, REG_MCUFW_CTRL, BIT_FWDL_CHK_RPT, 1)) {
903 rtw_err(rtwdev, "failed to check download firmware report\n");
910 static int download_firmware_validate_legacy(struct rtw_dev *rtwdev)
915 val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL);
918 rtw_write32(rtwdev, REG_MCUFW_CTRL, val32);
920 wlan_cpu_enable(rtwdev, false);
921 wlan_cpu_enable(rtwdev, true);
924 val32 = rtw_read32(rtwdev, REG_MCUFW_CTRL);
930 rtw_err(rtwdev, "failed to validate firmware\n");
934 static int __rtw_download_firmware_legacy(struct rtw_dev *rtwdev,
939 en_download_firmware_legacy(rtwdev, true);
940 ret = download_firmware_legacy(rtwdev, fw->firmware->data, fw->firmware->size);
941 en_download_firmware_legacy(rtwdev, false);
945 ret = download_firmware_validate_legacy(rtwdev);
950 rtw_hci_setup(rtwdev);
952 rtwdev->h2c.last_box_num = 0;
953 rtwdev->h2c.seq = 0;
955 set_bit(RTW_FLAG_FW_RUNNING, rtwdev->flags);
962 int _rtw_download_firmware(struct rtw_dev *rtwdev, struct rtw_fw_state *fw)
964 if (rtw_chip_wcpu_11n(rtwdev))
965 return __rtw_download_firmware_legacy(rtwdev, fw);
967 return __rtw_download_firmware(rtwdev, fw);
970 int rtw_download_firmware(struct rtw_dev *rtwdev, struct rtw_fw_state *fw)
974 ret = _rtw_download_firmware(rtwdev, fw);
978 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_PCIE &&
979 rtwdev->chip->id == RTW_CHIP_TYPE_8821C)
980 rtw_fw_set_recover_bt_device(rtwdev);
985 static u32 get_priority_queues(struct rtw_dev *rtwdev, u32 queues)
987 const struct rtw_rqpn *rqpn = rtwdev->fifo.rqpn;
1002 static void __rtw_mac_flush_prio_queue(struct rtw_dev *rtwdev,
1005 const struct rtw_chip_info *chip = rtwdev->chip;
1019 rsvd_page = wsize ? rtw_read16(rtwdev, addr->rsvd) :
1020 rtw_read8(rtwdev, addr->rsvd);
1021 avail_page = wsize ? rtw_read16(rtwdev, addr->avail) :
1022 rtw_read8(rtwdev, addr->avail);
1036 rtw_warn(rtwdev, "timed out to flush queue %d\n", prio_queue);
1039 static void rtw_mac_flush_prio_queues(struct rtw_dev *rtwdev,
1046 __rtw_mac_flush_prio_queue(rtwdev, q, drop);
1049 void rtw_mac_flush_queues(struct rtw_dev *rtwdev, u32 queues, bool drop)
1057 if (queues == BIT(rtwdev->hw->queues) - 1 || !rtwdev->fifo.rqpn)
1060 prio_queues = get_priority_queues(rtwdev, queues);
1062 rtw_mac_flush_prio_queues(rtwdev, prio_queues, drop);
1065 static int txdma_queue_mapping(struct rtw_dev *rtwdev)
1067 const struct rtw_chip_info *chip = rtwdev->chip;
1071 switch (rtw_hci_type(rtwdev)) {
1076 if (rtwdev->hci.bulkout_num == 2)
1078 else if (rtwdev->hci.bulkout_num == 3)
1080 else if (rtwdev->hci.bulkout_num == 4)
1092 rtwdev->fifo.rqpn = rqpn;
1099 rtw_write16(rtwdev, REG_TXDMA_PQ_MAP, txdma_pq_map);
1101 rtw_write8(rtwdev, REG_CR, 0);
1102 rtw_write8(rtwdev, REG_CR, MAC_TRX_ENABLE);
1103 if (rtw_chip_wcpu_11ac(rtwdev))
1104 rtw_write32(rtwdev, REG_H2CQ_CSR, BIT_H2CQ_FULL);
1106 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_SDIO) {
1107 rtw_read32(rtwdev, REG_SDIO_FREE_TXPG);
1108 rtw_write32(rtwdev, REG_SDIO_TX_CTRL, 0);
1109 } else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB) {
1110 rtw_write8_set(rtwdev, REG_TXDMA_PQ_MAP, BIT_RXDMA_ARBBW_EN);
1116 static int set_trx_fifo_info(struct rtw_dev *rtwdev)
1118 const struct rtw_chip_info *chip = rtwdev->chip;
1119 struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1126 if (rtw_chip_wcpu_11n(rtwdev))
1144 if (rtw_chip_wcpu_11ac(rtwdev)) {
1162 rtw_err(rtwdev, "wrong rsvd driver address\n");
1169 static int __priority_queue_cfg(struct rtw_dev *rtwdev,
1173 const struct rtw_chip_info *chip = rtwdev->chip;
1174 struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1176 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_1, pg_tbl->hq_num);
1177 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_2, pg_tbl->lq_num);
1178 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_3, pg_tbl->nq_num);
1179 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_4, pg_tbl->exq_num);
1180 rtw_write16(rtwdev, REG_FIFOPAGE_INFO_5, pubq_num);
1181 rtw_write32_set(rtwdev, REG_RQPN_CTRL_2, BIT_LD_RQPN);
1183 rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2, fifo->rsvd_boundary);
1184 rtw_write8_set(rtwdev, REG_FWHW_TXQ_CTRL + 2, BIT_EN_WR_FREE_TAIL >> 16);
1186 rtw_write16(rtwdev, REG_BCNQ_BDNY_V1, fifo->rsvd_boundary);
1187 rtw_write16(rtwdev, REG_FIFOPAGE_CTRL_2 + 2, fifo->rsvd_boundary);
1188 rtw_write16(rtwdev, REG_BCNQ1_BDNY_V1, fifo->rsvd_boundary);
1189 rtw_write32(rtwdev, REG_RXFF_BNDY, chip->rxff_size - C2H_PKT_BUF - 1);
1190 rtw_write8_set(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1);
1192 if (!check_hw_ready(rtwdev, REG_AUTO_LLT_V1, BIT_AUTO_INIT_LLT_V1, 0))
1195 rtw_write8(rtwdev, REG_CR + 3, 0);
1200 static int __priority_queue_cfg_legacy(struct rtw_dev *rtwdev,
1204 const struct rtw_chip_info *chip = rtwdev->chip;
1205 struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1209 rtw_write32(rtwdev, REG_RQPN_NPQ, val32);
1211 rtw_write32(rtwdev, REG_RQPN, val32);
1213 rtw_write8(rtwdev, REG_TRXFF_BNDY, fifo->rsvd_boundary);
1214 rtw_write16(rtwdev, REG_TRXFF_BNDY + 2, chip->rxff_size - REPORT_BUF - 1);
1215 rtw_write8(rtwdev, REG_DWBCN0_CTRL + 1, fifo->rsvd_boundary);
1216 rtw_write8(rtwdev, REG_BCNQ_BDNY, fifo->rsvd_boundary);
1217 rtw_write8(rtwdev, REG_MGQ_BDNY, fifo->rsvd_boundary);
1218 rtw_write8(rtwdev, REG_WMAC_LBK_BF_HD, fifo->rsvd_boundary);
1220 rtw_write32_set(rtwdev, REG_AUTO_LLT, BIT_AUTO_INIT_LLT);
1222 if (!check_hw_ready(rtwdev, REG_AUTO_LLT, BIT_AUTO_INIT_LLT, 0))
1228 static int priority_queue_cfg(struct rtw_dev *rtwdev)
1230 const struct rtw_chip_info *chip = rtwdev->chip;
1231 struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1236 ret = set_trx_fifo_info(rtwdev);
1240 switch (rtw_hci_type(rtwdev)) {
1245 if (rtwdev->hci.bulkout_num == 2)
1247 else if (rtwdev->hci.bulkout_num == 3)
1249 else if (rtwdev->hci.bulkout_num == 4)
1263 if (rtw_chip_wcpu_11n(rtwdev))
1264 return __priority_queue_cfg_legacy(rtwdev, pg_tbl, pubq_num);
1266 return __priority_queue_cfg(rtwdev, pg_tbl, pubq_num);
1269 static int init_h2c(struct rtw_dev *rtwdev)
1271 struct rtw_fifo_conf *fifo = &rtwdev->fifo;
1279 if (rtw_chip_wcpu_11n(rtwdev))
1285 value32 = rtw_read32(rtwdev, REG_H2C_HEAD);
1287 rtw_write32(rtwdev, REG_H2C_HEAD, value32);
1289 value32 = rtw_read32(rtwdev, REG_H2C_READ_ADDR);
1291 rtw_write32(rtwdev, REG_H2C_READ_ADDR, value32);
1293 value32 = rtw_read32(rtwdev, REG_H2C_TAIL);
1296 rtw_write32(rtwdev, REG_H2C_TAIL, value32);
1298 value8 = rtw_read8(rtwdev, REG_H2C_INFO);
1300 rtw_write8(rtwdev, REG_H2C_INFO, value8);
1302 value8 = rtw_read8(rtwdev, REG_H2C_INFO);
1304 rtw_write8(rtwdev, REG_H2C_INFO, value8);
1306 value8 = rtw_read8(rtwdev, REG_TXDMA_OFFSET_CHK + 1);
1308 rtw_write8(rtwdev, REG_TXDMA_OFFSET_CHK + 1, value8);
1310 wp = rtw_read32(rtwdev, REG_H2C_PKT_WRITEADDR) & 0x3FFFF;
1311 rp = rtw_read32(rtwdev, REG_H2C_PKT_READADDR) & 0x3FFFF;
1315 rtw_err(rtwdev, "H2C queue mismatch\n");
1322 static int rtw_init_trx_cfg(struct rtw_dev *rtwdev)
1326 ret = txdma_queue_mapping(rtwdev);
1330 ret = priority_queue_cfg(rtwdev);
1334 ret = init_h2c(rtwdev);
1341 static int rtw_drv_info_cfg(struct rtw_dev *rtwdev)
1345 rtw_write8(rtwdev, REG_RX_DRVINFO_SZ, PHY_STATUS_SIZE);
1346 if (rtw_chip_wcpu_11ac(rtwdev)) {
1347 value8 = rtw_read8(rtwdev, REG_TRXFF_BNDY + 1);
1351 rtw_write8(rtwdev, REG_TRXFF_BNDY + 1, value8);
1353 rtw_write32_set(rtwdev, REG_RCR, BIT_APP_PHYSTS);
1354 rtw_write32_clr(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, BIT(8) | BIT(9));
1359 int rtw_mac_init(struct rtw_dev *rtwdev)
1361 const struct rtw_chip_info *chip = rtwdev->chip;
1364 ret = rtw_init_trx_cfg(rtwdev);
1368 ret = chip->ops->mac_init(rtwdev);
1372 ret = rtw_drv_info_cfg(rtwdev);
1376 rtw_hci_interface_cfg(rtwdev);