Lines Matching refs:rt2x00dev
64 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
67 if (!rt2x00_is_soc(rt2x00dev) ||
68 !rt2x00_rt(rt2x00dev, RT2872))
72 if (rt2x00_rf(rt2x00dev, RF3020) ||
73 rt2x00_rf(rt2x00dev, RF3021) ||
74 rt2x00_rf(rt2x00dev, RF3022))
77 rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
81 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
86 mutex_lock(&rt2x00dev->csr_mutex);
92 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
100 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
103 mutex_unlock(&rt2x00dev->csr_mutex);
106 static u8 rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, const unsigned int word)
111 mutex_lock(&rt2x00dev->csr_mutex);
121 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
128 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
130 WAIT_FOR_BBP(rt2x00dev, ®);
135 mutex_unlock(&rt2x00dev->csr_mutex);
140 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 mutex_lock(&rt2x00dev->csr_mutex);
151 switch (rt2x00dev->chip.rt) {
153 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) {
161 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
166 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) {
173 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
178 mutex_unlock(&rt2x00dev->csr_mutex);
181 static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
184 rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value);
187 static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev,
190 rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value);
191 rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value);
194 static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev,
197 rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value);
198 rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value);
201 static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev,
204 rt2800_bbp_write(rt2x00dev, 158, reg);
205 rt2800_bbp_write(rt2x00dev, 159, value);
208 static u8 rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev, const u8 reg)
210 rt2800_bbp_write(rt2x00dev, 158, reg);
211 return rt2800_bbp_read(rt2x00dev, 159);
214 static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev,
217 rt2800_bbp_write(rt2x00dev, 195, reg);
218 rt2800_bbp_write(rt2x00dev, 196, value);
221 static u8 rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
227 mutex_lock(&rt2x00dev->csr_mutex);
237 switch (rt2x00dev->chip.rt) {
239 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®)) {
246 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
248 WAIT_FOR_RFCSR_MT7620(rt2x00dev, ®);
255 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) {
261 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
263 WAIT_FOR_RFCSR(rt2x00dev, ®);
270 mutex_unlock(&rt2x00dev->csr_mutex);
275 static u8 rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
278 return rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6)));
281 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
286 mutex_lock(&rt2x00dev->csr_mutex);
292 if (WAIT_FOR_RF(rt2x00dev, ®)) {
299 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
300 rt2x00_rf_write(rt2x00dev, word, value);
303 mutex_unlock(&rt2x00dev->csr_mutex);
386 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
394 wiphy_name(rt2x00dev->hw->wiphy), word))
397 if (rt2x00_rt(rt2x00dev, RT3593) ||
398 rt2x00_rt(rt2x00dev, RT3883))
413 wiphy_name(rt2x00dev->hw->wiphy), word);
418 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
423 index = rt2800_eeprom_word_index(rt2x00dev, word);
424 return rt2x00_eeprom_addr(rt2x00dev, index);
427 static u16 rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
432 index = rt2800_eeprom_word_index(rt2x00dev, word);
433 return rt2x00_eeprom_read(rt2x00dev, index);
436 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
441 index = rt2800_eeprom_word_index(rt2x00dev, word);
442 rt2x00_eeprom_write(rt2x00dev, index, data);
445 static u16 rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
451 index = rt2800_eeprom_word_index(rt2x00dev, array);
452 return rt2x00_eeprom_read(rt2x00dev, index + offset);
455 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
460 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
465 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
475 reg = rt2800_register_read(rt2x00dev, CMB_CTRL);
487 rt2800_register_write(rt2x00dev, 0x58, 0x018);
489 rt2800_register_write(rt2x00dev, 0x58, 0x418);
491 rt2800_register_write(rt2x00dev, 0x58, 0x618);
498 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
502 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
505 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
507 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
513 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
522 if (rt2x00_is_soc(rt2x00dev))
525 mutex_lock(&rt2x00dev->csr_mutex);
531 if (WAIT_FOR_MCU(rt2x00dev, ®)) {
536 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
540 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
543 mutex_unlock(&rt2x00dev->csr_mutex);
547 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
553 reg = rt2800_register_read(rt2x00dev, MAC_CSR0);
559 rt2x00_err(rt2x00dev, "Unstable hardware\n");
564 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
574 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
582 rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
587 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
591 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
597 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
601 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
605 switch (rt2x00dev->chip.rt) {
658 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
674 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
690 if (rt2x00_is_usb(rt2x00dev) &&
691 !rt2x00_rt(rt2x00dev, RT2860) &&
692 !rt2x00_rt(rt2x00dev, RT2872) &&
693 !rt2x00_rt(rt2x00dev, RT3070) &&
712 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
719 if (rt2x00_rt(rt2x00dev, RT3290)) {
720 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
729 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
734 if (rt2800_wait_csr_ready(rt2x00dev))
737 if (rt2x00_is_pci(rt2x00dev)) {
738 if (rt2x00_rt(rt2x00dev, RT3290) ||
739 rt2x00_rt(rt2x00dev, RT3572) ||
740 rt2x00_rt(rt2x00dev, RT5390) ||
741 rt2x00_rt(rt2x00dev, RT5392)) {
742 reg = rt2800_register_read(rt2x00dev, AUX_CTRL);
745 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
747 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
750 rt2800_disable_wpdma(rt2x00dev);
755 rt2800_drv_write_firmware(rt2x00dev, data, len);
761 reg = rt2800_register_read(rt2x00dev, PBF_SYS_CTRL);
768 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
776 rt2800_disable_wpdma(rt2x00dev);
781 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
782 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
783 if (rt2x00_is_usb(rt2x00dev)) {
784 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
785 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
854 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
864 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
865 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG);
868 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
871 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A);
874 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
883 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
884 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
885 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
934 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
1007 rt2x00_dbg(entry->queue->rt2x00dev,
1019 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1020 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1062 rt2800_rate_from_status(skbdesc, status, rt2x00dev->curr_band);
1093 txdesc.retry = rt2x00dev->long_retry;
1118 void rt2800_txdone(struct rt2x00_dev *rt2x00dev, unsigned int quota)
1126 while (quota-- > 0 && kfifo_get(&rt2x00dev->txstatus_fifo, ®)) {
1132 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
1135 rt2x00_dbg(rt2x00dev, "Got TX status for an empty queue %u, dropping\n",
1144 rt2x00_warn(rt2x00dev, "Data pending for entry %u in queue %u\n",
1155 static inline bool rt2800_entry_txstatus_timeout(struct rt2x00_dev *rt2x00dev,
1164 if (test_bit(DEVICE_STATE_FLUSHING, &rt2x00dev->flags))
1171 rt2x00_dbg(entry->queue->rt2x00dev,
1177 bool rt2800_txstatus_timeout(struct rt2x00_dev *rt2x00dev)
1182 tx_queue_for_each(rt2x00dev, queue) {
1184 if (rt2800_entry_txstatus_timeout(rt2x00dev, entry))
1196 bool rt2800_txstatus_pending(struct rt2x00_dev *rt2x00dev)
1200 tx_queue_for_each(rt2x00dev, queue) {
1209 void rt2800_txdone_nostatus(struct rt2x00_dev *rt2x00dev)
1221 tx_queue_for_each(rt2x00dev, queue) {
1230 rt2800_entry_txstatus_timeout(rt2x00dev, entry))
1251 static void rt2800_update_survey(struct rt2x00_dev *rt2x00dev)
1253 struct ieee80211_channel *chan = rt2x00dev->hw->conf.chandef.chan;
1255 &rt2x00dev->chan_survey[chan->hw_value];
1257 chan_survey->time_idle += rt2800_register_read(rt2x00dev, CH_IDLE_STA);
1258 chan_survey->time_busy += rt2800_register_read(rt2x00dev, CH_BUSY_STA);
1259 chan_survey->time_ext_busy += rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC);
1262 void rt2800_watchdog(struct rt2x00_dev *rt2x00dev)
1268 if (test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags))
1271 rt2800_update_survey(rt2x00dev);
1273 queue_for_each(rt2x00dev, queue) {
1289 if (rt2x00dev->intf_sta_count == 0)
1299 rt2x00_warn(rt2x00dev, "Watchdog TX hung detected\n");
1302 rt2x00_warn(rt2x00dev, "Watchdog RX hung detected\n");
1305 ieee80211_restart_hw(rt2x00dev->hw);
1309 static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
1315 static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
1318 return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
1321 static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev)
1323 struct data_queue *queue = rt2x00dev->bcn;
1336 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx);
1341 rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg);
1342 rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32));
1347 bssid_dw1 = rt2800_register_read(rt2x00dev, MAC_BSSID_DW1);
1350 rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1);
1355 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1366 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1369 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1391 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry);
1398 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
1401 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1405 beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
1407 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1414 rt2800_update_beacons_setup(rt2x00dev);
1419 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1429 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
1433 const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
1436 beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
1444 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1449 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1456 orig_reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1459 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1464 rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
1470 rt2800_update_beacons_setup(rt2x00dev);
1474 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1524 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1528 if (rt2x00_rt(rt2x00dev, RT3290)) {
1529 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
1532 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
1546 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ);
1548 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1551 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1556 if (rt2x00_is_soc(led->rt2x00dev)) {
1557 reg = rt2800_register_read(led->rt2x00dev, LED_CFG);
1574 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1578 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1581 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1592 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1599 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
1602 led->rt2x00dev = rt2x00dev;
1612 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1625 rt2800_register_multiwrite(rt2x00dev, offset,
1629 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1633 rt2800_register_write(rt2x00dev, offset, 0);
1636 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1646 reg = rt2800_register_read(rt2x00dev, offset);
1650 rt2800_register_write(rt2x00dev, offset, reg);
1653 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1664 reg = rt2800_register_read(rt2x00dev, offset);
1677 rt2800_register_write(rt2x00dev, offset, reg);
1680 reg = rt2800_register_read(rt2x00dev, offset);
1685 rt2800_register_write(rt2x00dev, offset, reg);
1688 if (test_bit(DEVICE_STATE_RESET, &rt2x00dev->flags))
1699 rt2800_register_multiwrite(rt2x00dev, offset,
1703 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1723 rt2800_register_multiwrite(rt2x00dev, offset,
1739 reg = rt2800_register_read(rt2x00dev, offset);
1742 rt2800_register_write(rt2x00dev, offset, reg);
1747 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1748 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1750 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1756 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1780 rt2800_register_multiwrite(rt2x00dev, offset,
1787 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1793 static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev)
1797 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1805 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG);
1807 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1813 struct rt2x00_dev *rt2x00dev = hw->priv;
1814 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1826 rt2800_set_max_psdu_len(rt2x00dev);
1854 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1855 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1856 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1857 rt2x00lib_get_bssidx(rt2x00dev, vif));
1865 struct rt2x00_dev *rt2x00dev = hw->priv;
1866 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1872 rt2800_set_max_psdu_len(rt2x00dev);
1881 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1889 void rt2800_pre_reset_hw(struct rt2x00_dev *rt2x00dev)
1891 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1892 struct data_queue *queue = rt2x00dev->bcn;
1908 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1919 reg = rt2800_register_read(rt2x00dev, RX_FILTER_CFG);
1925 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
1949 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1953 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1963 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1965 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1971 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG);
1976 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1978 reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG);
1983 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
2004 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
2016 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
2022 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
2097 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
2100 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2102 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
2105 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2107 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
2110 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2112 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
2115 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2118 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
2124 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG);
2127 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
2131 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
2134 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2138 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
2140 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2144 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG);
2147 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2149 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG);
2151 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
2155 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
2158 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2162 rt2800_config_ht_opmode(rt2x00dev, erp);
2166 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev,
2173 reg = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
2180 rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
2184 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
2193 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
2194 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
2198 value = rt2800_bbp_read(rt2x00dev, 0);
2204 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
2208 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
2214 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
2215 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {
2222 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
2224 reg = rt2800_register_read(rt2x00dev, LED_CFG);
2229 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
2234 rt2800_register_write(rt2x00dev, LED_CFG, reg);
2236 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
2242 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
2249 if (rt2x00_is_pci(rt2x00dev)) {
2250 reg = rt2800_register_read(rt2x00dev, E2PROM_CSR);
2252 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
2253 } else if (rt2x00_is_usb(rt2x00dev))
2254 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
2257 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
2260 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2263 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
2269 r1 = rt2800_bbp_read(rt2x00dev, 1);
2270 r3 = rt2800_bbp_read(rt2x00dev, 3);
2272 if (rt2x00_rt(rt2x00dev, RT3572) &&
2273 rt2x00_has_cap_bt_coexist(rt2x00dev))
2274 rt2800_config_3572bt_ant(rt2x00dev);
2284 if (rt2x00_rt(rt2x00dev, RT3572) &&
2285 rt2x00_has_cap_bt_coexist(rt2x00dev))
2300 if (rt2x00_rt(rt2x00dev, RT3070) ||
2301 rt2x00_rt(rt2x00dev, RT3090) ||
2302 rt2x00_rt(rt2x00dev, RT3352) ||
2303 rt2x00_rt(rt2x00dev, RT3390)) {
2304 eeprom = rt2800_eeprom_read(rt2x00dev,
2308 rt2800_set_ant_diversity(rt2x00dev,
2309 rt2x00dev->default_ant.rx);
2314 if (rt2x00_rt(rt2x00dev, RT3572) &&
2315 rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2318 rt2x00dev->curr_band == NL80211_BAND_5GHZ);
2319 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
2329 rt2800_bbp_write(rt2x00dev, 3, r3);
2330 rt2800_bbp_write(rt2x00dev, 1, r1);
2332 if (rt2x00_rt(rt2x00dev, RT3593) ||
2333 rt2x00_rt(rt2x00dev, RT3883)) {
2335 rt2800_bbp_write(rt2x00dev, 86, 0x00);
2337 rt2800_bbp_write(rt2x00dev, 86, 0x46);
2342 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
2349 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
2352 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
2355 if (rt2x00_rt(rt2x00dev, RT3593) ||
2356 rt2x00_rt(rt2x00dev, RT3883)) {
2357 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
2361 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
2366 if (rt2x00_rt(rt2x00dev, RT3593) ||
2367 rt2x00_rt(rt2x00dev, RT3883)) {
2368 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
2372 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
2378 rt2x00dev->lna_gain = lna_gain;
2381 static inline bool rt2800_clk_is_20mhz(struct rt2x00_dev *rt2x00dev)
2383 return clk_get_rate(rt2x00dev->clk) == 20000000;
2388 static void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev)
2393 freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
2396 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
2403 if (rt2x00_is_usb(rt2x00dev)) {
2404 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
2417 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2423 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
2428 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
2430 if (rt2x00dev->default_ant.tx_chain_num == 1)
2433 if (rt2x00dev->default_ant.rx_chain_num == 1) {
2436 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
2468 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2469 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2470 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2471 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2475 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2476 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2477 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
2478 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2482 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2483 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2484 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2485 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2488 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
2493 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2496 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2498 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
2500 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2502 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2504 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2506 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2508 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2510 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
2512 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2514 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2517 rt2x00dev->default_ant.rx_chain_num <= 1);
2519 rt2x00dev->default_ant.rx_chain_num <= 2);
2522 rt2x00dev->default_ant.tx_chain_num <= 1);
2524 rt2x00dev->default_ant.tx_chain_num <= 2);
2525 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2527 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
2528 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2529 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2531 if (rt2x00_rt(rt2x00dev, RT3390)) {
2544 rfcsr = rt2800_rfcsr_read(rt2x00dev, 24);
2546 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2548 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
2550 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2552 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2554 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2556 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2558 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2563 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2566 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2571 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2576 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2577 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2579 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2580 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2583 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2584 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2586 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2592 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2594 rfcsr = rt2800_rfcsr_read(rt2x00dev, 5);
2599 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2601 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2612 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2614 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
2625 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2627 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2634 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2642 switch (rt2x00dev->default_ant.tx_chain_num) {
2651 switch (rt2x00dev->default_ant.rx_chain_num) {
2660 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2662 rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
2663 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2664 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2667 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2668 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2670 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2671 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2675 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2676 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2677 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2678 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2679 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2683 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2684 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2685 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2686 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2687 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2688 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2689 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2690 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2692 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2697 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2698 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2699 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2700 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2701 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
2705 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2706 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2708 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2709 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2710 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2712 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2713 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2714 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2716 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2717 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2718 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2720 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2721 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2722 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2725 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
2731 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2733 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2735 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2738 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
2743 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2751 bbp = rt2800_bbp_read(rt2x00dev, 109);
2754 rt2800_bbp_write(rt2x00dev, 109, bbp);
2756 bbp = rt2800_bbp_read(rt2x00dev, 110);
2758 rt2800_bbp_write(rt2x00dev, 110, bbp);
2762 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2763 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2768 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2770 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2773 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2774 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2776 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2778 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2780 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2786 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2788 rfcsr = rt2800_rfcsr_read(rt2x00dev, 53);
2794 if (rt2x00_is_usb(rt2x00dev))
2801 rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2803 rfcsr = rt2800_rfcsr_read(rt2x00dev, 55);
2809 if (rt2x00_is_usb(rt2x00dev))
2816 rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2818 rfcsr = rt2800_rfcsr_read(rt2x00dev, 54);
2824 if (rt2x00_is_usb(rt2x00dev))
2831 rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2833 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2843 switch (rt2x00dev->default_ant.tx_chain_num) {
2855 switch (rt2x00dev->default_ant.rx_chain_num) {
2866 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2868 rt2800_freq_cal_mode1(rt2x00dev);
2885 rfcsr = rt2800_rfcsr_read(rt2x00dev, 32);
2892 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2894 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2897 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2900 rfcsr = rt2800_rfcsr_read(rt2x00dev, 36);
2905 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2907 rfcsr = rt2800_rfcsr_read(rt2x00dev, 34);
2912 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2914 rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2919 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2921 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2930 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2932 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2934 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2936 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2939 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2940 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2942 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
2943 rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
2946 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
2948 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2950 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
2958 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2960 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
2969 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2971 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
2973 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2975 rfcsr = rt2800_rfcsr_read(rt2x00dev, 57);
2980 rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
2983 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
2984 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
2986 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
2987 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
2991 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3002 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3008 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3010 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
3015 rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
3017 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
3022 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3024 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
3029 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3031 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
3035 static void rt2800_config_channel_rf3853(struct rt2x00_dev *rt2x00dev,
3049 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
3051 rt2800_rfcsr_write(rt2x00dev, 6, 0x80);
3053 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
3055 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3056 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3059 rt2800_rfcsr_write(rt2x00dev, 11, 0x46);
3061 rt2800_rfcsr_write(rt2x00dev, 11, 0x48);
3064 rt2800_rfcsr_write(rt2x00dev, 12, 0x1a);
3066 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
3068 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
3070 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3080 switch (rt2x00dev->default_ant.tx_chain_num) {
3092 switch (rt2x00dev->default_ant.rx_chain_num) {
3103 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3105 rt2800_freq_cal_mode1(rt2x00dev);
3107 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
3112 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3115 rt2800_rfcsr_write(rt2x00dev, 31, 0xa0);
3117 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3120 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3122 rt2800_rfcsr_write(rt2x00dev, 32, 0xd8);
3125 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
3127 rt2800_rfcsr_write(rt2x00dev, 34, 0x20);
3130 rfcsr = rt2800_rfcsr_read(rt2x00dev, 36);
3135 rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
3149 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
3152 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
3154 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
3164 rt2800_rfcsr_write(rt2x00dev, 45, rfcsr);
3174 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3176 rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
3178 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
3180 rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
3182 rt2800_rfcsr_write(rt2x00dev, 51, 0x51);
3184 rfcsr = rt2800_rfcsr_read(rt2x00dev, 52);
3186 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
3188 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
3203 rt2800_rfcsr_write(rt2x00dev, 53, pwr1);
3204 rt2800_rfcsr_write(rt2x00dev, 54, pwr2);
3205 rt2800_rfcsr_write(rt2x00dev, 55, pwr3);
3207 rt2x00_dbg(rt2x00dev, "Channel:%d, pwr1:%02x, pwr2:%02x, pwr3:%02x\n",
3212 rt2800_bbp_write(rt2x00dev, 109, bbp);
3214 bbp = rt2800_bbp_read(rt2x00dev, 110);
3217 rt2800_bbp_write(rt2x00dev, 110, bbp);
3219 rfcsr = rt2800_rfcsr_read(rt2x00dev, 57);
3221 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
3223 rt2800_rfcsr_write(rt2x00dev, 57, 0x3e);
3226 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3228 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3232 bbp = rt2800_bbp_read(rt2x00dev, 49);
3234 rt2800_bbp_write(rt2x00dev, 49, bbp & 0xfe);
3235 rt2800_bbp_write(rt2x00dev, 49, bbp);
3243 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
3250 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3251 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3252 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3254 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3256 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3261 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3263 rt2800_freq_cal_mode1(rt2x00dev);
3267 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
3269 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
3272 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
3274 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
3276 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
3280 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
3287 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3288 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3290 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
3291 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
3292 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
3295 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
3297 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
3300 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
3302 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
3304 rt2800_freq_cal_mode1(rt2x00dev);
3306 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3310 if ( rt2x00dev->default_ant.tx_chain_num == 2 )
3315 if ( rt2x00dev->default_ant.rx_chain_num == 2 )
3323 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3325 rt2800_rfcsr_write(rt2x00dev, 31, 80);
3328 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
3336 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
3337 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
3338 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3340 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3342 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3347 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3349 if (rt2x00_rt(rt2x00dev, RT5392)) {
3350 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
3356 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
3359 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3360 if (rt2x00_rt(rt2x00dev, RT5392)) {
3368 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3370 rt2800_freq_cal_mode1(rt2x00dev);
3372 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
3373 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
3382 rt2800_rfcsr_write(rt2x00dev, 55,
3384 rt2800_rfcsr_write(rt2x00dev, 59,
3391 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
3394 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
3402 rt2800_rfcsr_write(rt2x00dev, 55,
3404 rt2800_rfcsr_write(rt2x00dev, 59,
3406 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
3407 rt2x00_rt(rt2x00dev, RT5392) ||
3408 rt2x00_rt(rt2x00dev, RT6352)) {
3413 rt2800_rfcsr_write(rt2x00dev, 59,
3415 } else if (rt2x00_rt(rt2x00dev, RT5350)) {
3420 rt2800_rfcsr_write(rt2x00dev, 59,
3426 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
3439 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
3442 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3445 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
3447 rfcsr = rt2800_rfcsr_read(rt2x00dev, 9);
3451 rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
3453 rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
3456 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
3459 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
3461 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
3462 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
3463 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
3464 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
3465 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
3466 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3467 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
3468 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
3469 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3470 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
3471 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
3472 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
3473 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
3474 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
3475 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
3476 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
3477 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
3478 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
3479 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3480 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
3481 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
3482 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
3483 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
3484 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
3485 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
3486 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3487 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
3488 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
3493 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
3494 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
3498 rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
3499 rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
3501 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
3503 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
3507 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
3509 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
3515 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
3517 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
3518 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
3519 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
3520 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3521 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
3522 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3523 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
3524 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
3525 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
3526 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
3527 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
3528 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
3529 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
3530 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
3536 rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
3537 rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
3538 rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
3539 rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
3541 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
3543 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
3544 rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
3545 rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
3546 rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
3547 rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
3548 rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
3549 rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
3550 rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
3552 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
3553 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
3555 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
3556 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
3559 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
3560 rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
3561 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
3565 rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
3566 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
3567 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
3569 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
3570 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
3572 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
3573 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
3576 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
3577 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
3578 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
3579 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
3581 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
3582 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
3583 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
3584 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
3587 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
3589 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
3591 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
3593 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
3594 rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
3596 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
3598 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
3600 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
3602 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
3604 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
3606 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
3608 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
3610 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
3612 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
3614 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
3621 rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3628 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3630 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
3637 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
3639 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3644 rt2x00dev->default_ant.tx_chain_num >= 1);
3646 rt2x00dev->default_ant.tx_chain_num == 2);
3650 rt2x00dev->default_ant.rx_chain_num >= 1);
3652 rt2x00dev->default_ant.rx_chain_num == 2);
3655 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3656 rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
3659 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
3661 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
3664 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3665 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3669 rt2800_freq_cal_mode1(rt2x00dev);
3672 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3674 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3677 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3678 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3679 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3681 rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
3682 rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
3683 rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
3684 rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
3687 rt2800_bbp_write(rt2x00dev, 195, 128);
3688 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
3689 rt2800_bbp_write(rt2x00dev, 195, 129);
3690 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
3691 rt2800_bbp_write(rt2x00dev, 195, 130);
3692 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
3693 rt2800_bbp_write(rt2x00dev, 195, 131);
3694 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
3695 rt2800_bbp_write(rt2x00dev, 195, 133);
3696 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
3697 rt2800_bbp_write(rt2x00dev, 195, 124);
3698 rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
3701 static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev,
3706 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
3714 rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
3716 rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0);
3717 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
3723 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
3725 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3727 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
3729 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3734 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
3736 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3741 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
3743 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3750 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
3752 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3754 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
3756 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
3758 rfcsr = rt2800_rfcsr_read(rt2x00dev, 19);
3760 rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
3763 rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
3765 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3767 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
3769 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3771 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3773 rt2x00dev->default_ant.tx_chain_num != 1);
3774 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3776 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
3778 rt2x00dev->default_ant.tx_chain_num != 1);
3780 rt2x00dev->default_ant.rx_chain_num != 1);
3781 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3783 rfcsr = rt2800_rfcsr_read(rt2x00dev, 42);
3785 rt2x00dev->default_ant.tx_chain_num != 1);
3786 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
3790 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
3791 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
3792 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
3793 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
3794 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
3796 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20);
3797 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20);
3798 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00);
3799 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20);
3800 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);
3804 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
3805 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
3807 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
3808 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
3811 rfcsr = rt2800_rfcsr_read(rt2x00dev, 28);
3814 rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
3816 if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) {
3824 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
3827 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr);
3828 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
3831 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr);
3832 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 6);
3835 rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr);
3836 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 7);
3839 rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr);
3841 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
3844 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr);
3845 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
3848 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr);
3849 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 58);
3852 rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr);
3853 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 59);
3856 rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr);
3860 rt2800_bbp_glrt_write(rt2x00dev, 141, 0x10);
3861 rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2f);
3863 rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1a);
3864 rt2800_bbp_glrt_write(rt2x00dev, 157, 0x40);
3868 static void rt2800_config_alc_rt6352(struct rt2x00_dev *rt2x00dev,
3872 int cur_channel = rt2x00dev->rf_channel;
3892 rate_power = rt2800_eeprom_read_from_array(rt2x00dev,
3899 power_group[0] = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
3900 power_group[1] = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
3908 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_0);
3914 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
3917 target_power = rt2800_eeprom_read(rt2x00dev,
3922 rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg);
3924 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
3926 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
3929 mac_sys_ctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
3931 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
3933 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY)))
3934 rt2x00_warn(rt2x00dev, "RF busy while configuring ALC\n");
3937 bbp = rt2800_bbp_read(rt2x00dev, 30);
3939 rt2800_bbp_write(rt2x00dev, 30, bbp);
3940 rt2800_rfcsr_write(rt2x00dev, 39, 0);
3941 if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
3942 rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
3944 rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
3946 bbp = rt2800_bbp_read(rt2x00dev, 30);
3948 rt2800_bbp_write(rt2x00dev, 30, bbp);
3949 rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
3950 if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
3951 rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
3953 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
3955 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);
3957 rt2800_vco_calibration(rt2x00dev);
3960 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
3966 for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
3967 reg = rt2800_bbp_read(rt2x00dev, 27);
3969 rt2800_bbp_write(rt2x00dev, 27, reg);
3971 rt2800_bbp_write(rt2x00dev, word, value);
3975 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
3980 rt2800_bbp_write(rt2x00dev, 158, 0x2c);
3982 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
3984 cal = rt2x00_eeprom_byte(rt2x00dev,
3987 cal = rt2x00_eeprom_byte(rt2x00dev,
3990 cal = rt2x00_eeprom_byte(rt2x00dev,
3994 rt2800_bbp_write(rt2x00dev, 159, cal);
3997 rt2800_bbp_write(rt2x00dev, 158, 0x2d);
3999 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
4001 cal = rt2x00_eeprom_byte(rt2x00dev,
4004 cal = rt2x00_eeprom_byte(rt2x00dev,
4007 cal = rt2x00_eeprom_byte(rt2x00dev,
4011 rt2800_bbp_write(rt2x00dev, 159, cal);
4014 rt2800_bbp_write(rt2x00dev, 158, 0x4a);
4016 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
4018 cal = rt2x00_eeprom_byte(rt2x00dev,
4021 cal = rt2x00_eeprom_byte(rt2x00dev,
4024 cal = rt2x00_eeprom_byte(rt2x00dev,
4028 rt2800_bbp_write(rt2x00dev, 159, cal);
4031 rt2800_bbp_write(rt2x00dev, 158, 0x4b);
4033 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
4035 cal = rt2x00_eeprom_byte(rt2x00dev,
4038 cal = rt2x00_eeprom_byte(rt2x00dev,
4041 cal = rt2x00_eeprom_byte(rt2x00dev,
4045 rt2800_bbp_write(rt2x00dev, 159, cal);
4050 rt2800_bbp_write(rt2x00dev, 158, 0x04);
4051 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
4052 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
4055 rt2800_bbp_write(rt2x00dev, 158, 0x03);
4056 cal = rt2x00_eeprom_byte(rt2x00dev,
4058 rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
4061 static s8 rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
4065 if (rt2x00_rt(rt2x00dev, RT3593) ||
4066 rt2x00_rt(rt2x00dev, RT3883))
4072 if (rt2x00_rt(rt2x00dev, RT3593) ||
4073 rt2x00_rt(rt2x00dev, RT3883))
4080 static void rt3883_bbp_adjust(struct rt2x00_dev *rt2x00dev,
4086 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, bbp);
4088 rt2800_bbp_write(rt2x00dev, 69, 0x12);
4091 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4094 rt2800_bbp_write(rt2x00dev, 70, 0x00);
4097 rt2800_bbp_write(rt2x00dev, 73, 0x10);
4100 rt2800_bbp_write(rt2x00dev, 62, 0x1d);
4101 rt2800_bbp_write(rt2x00dev, 63, 0x1d);
4102 rt2800_bbp_write(rt2x00dev, 64, 0x1d);
4104 rt2800_bbp_write(rt2x00dev, 62, 0x2d);
4105 rt2800_bbp_write(rt2x00dev, 63, 0x2d);
4106 rt2800_bbp_write(rt2x00dev, 64, 0x2d);
4110 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
4119 info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
4121 info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
4123 if (rt2x00dev->default_ant.tx_chain_num > 2)
4125 rt2800_txpower_to_dev(rt2x00dev, rf->channel,
4128 switch (rt2x00dev->chip.rt) {
4130 rt3883_bbp_adjust(rt2x00dev, rf);
4134 switch (rt2x00dev->chip.rf) {
4140 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
4143 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
4146 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
4149 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
4152 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
4155 rt2800_config_channel_rf3853(rt2x00dev, conf, rf, info);
4165 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
4168 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
4171 rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info);
4174 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
4177 if (rt2x00_rf(rt2x00dev, RF3070) ||
4178 rt2x00_rf(rt2x00dev, RF3290) ||
4179 rt2x00_rf(rt2x00dev, RF3322) ||
4180 rt2x00_rf(rt2x00dev, RF5350) ||
4181 rt2x00_rf(rt2x00dev, RF5360) ||
4182 rt2x00_rf(rt2x00dev, RF5362) ||
4183 rt2x00_rf(rt2x00dev, RF5370) ||
4184 rt2x00_rf(rt2x00dev, RF5372) ||
4185 rt2x00_rf(rt2x00dev, RF5390) ||
4186 rt2x00_rf(rt2x00dev, RF5392)) {
4187 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
4188 if (rt2x00_rf(rt2x00dev, RF3322)) {
4199 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4201 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
4203 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
4210 if (rt2x00_rt(rt2x00dev, RT3352)) {
4211 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4212 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4213 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4215 rt2800_bbp_write(rt2x00dev, 27, 0x0);
4216 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
4217 rt2800_bbp_write(rt2x00dev, 27, 0x20);
4218 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
4219 rt2800_bbp_write(rt2x00dev, 86, 0x38);
4220 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
4221 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
4224 rt2800_bbp_write(rt2x00dev, 70, 0x00);
4226 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4230 rt2800_bbp_write(rt2x00dev, 105, 0x04);
4232 rt2800_bbp_write(rt2x00dev, 105, 0x34);
4234 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4235 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4236 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4237 rt2800_bbp_write(rt2x00dev, 77, 0x98);
4238 } else if (rt2x00_rt(rt2x00dev, RT3883)) {
4239 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4240 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4241 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4243 if (rt2x00dev->default_ant.rx_chain_num > 1)
4244 rt2800_bbp_write(rt2x00dev, 86, 0x46);
4246 rt2800_bbp_write(rt2x00dev, 86, 0);
4248 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
4249 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
4250 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
4251 if (rt2x00_rt(rt2x00dev, RT6352))
4252 rt2800_bbp_write(rt2x00dev, 86, 0x38);
4254 rt2800_bbp_write(rt2x00dev, 86, 0);
4258 if (!rt2x00_rt(rt2x00dev, RT5390) &&
4259 !rt2x00_rt(rt2x00dev, RT5392) &&
4260 !rt2x00_rt(rt2x00dev, RT6352)) {
4261 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
4262 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4263 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4264 rt2800_bbp_write(rt2x00dev, 75, 0x46);
4266 if (rt2x00_rt(rt2x00dev, RT3593))
4267 rt2800_bbp_write(rt2x00dev, 82, 0x62);
4269 rt2800_bbp_write(rt2x00dev, 82, 0x84);
4270 rt2800_bbp_write(rt2x00dev, 75, 0x50);
4272 if (rt2x00_rt(rt2x00dev, RT3593) ||
4273 rt2x00_rt(rt2x00dev, RT3883))
4274 rt2800_bbp_write(rt2x00dev, 83, 0x8a);
4278 if (rt2x00_rt(rt2x00dev, RT3572))
4279 rt2800_bbp_write(rt2x00dev, 82, 0x94);
4280 else if (rt2x00_rt(rt2x00dev, RT3593) ||
4281 rt2x00_rt(rt2x00dev, RT3883))
4282 rt2800_bbp_write(rt2x00dev, 82, 0x82);
4283 else if (!rt2x00_rt(rt2x00dev, RT6352))
4284 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
4286 if (rt2x00_rt(rt2x00dev, RT3593) ||
4287 rt2x00_rt(rt2x00dev, RT3883))
4288 rt2800_bbp_write(rt2x00dev, 83, 0x9a);
4290 if (rt2x00_has_cap_external_lna_a(rt2x00dev))
4291 rt2800_bbp_write(rt2x00dev, 75, 0x46);
4293 rt2800_bbp_write(rt2x00dev, 75, 0x50);
4296 reg = rt2800_register_read(rt2x00dev, TX_BAND_CFG);
4300 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
4302 if (rt2x00_rt(rt2x00dev, RT3572))
4303 rt2800_rfcsr_write(rt2x00dev, 8, 0);
4305 if (rt2x00_rt(rt2x00dev, RT6352)) {
4306 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
4312 switch (rt2x00dev->default_ant.tx_chain_num) {
4331 if (rt2x00_has_cap_bt_coexist(rt2x00dev))
4339 switch (rt2x00dev->default_ant.rx_chain_num) {
4360 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4362 if (rt2x00_rt(rt2x00dev, RT3572)) {
4363 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
4367 reg = 0x1c + (2 * rt2x00dev->lna_gain);
4369 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
4371 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4374 if (rt2x00_rt(rt2x00dev, RT3593)) {
4375 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
4378 if (rt2x00_is_usb(rt2x00dev) ||
4379 rt2x00_is_pcie(rt2x00dev)) {
4389 if (rt2x00_is_usb(rt2x00dev)) {
4398 } else if (rt2x00_is_pcie(rt2x00dev)) {
4404 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
4408 reg = 0x1c + 2 * rt2x00dev->lna_gain;
4410 reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
4412 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4417 if (rt2x00_rt(rt2x00dev, RT3883)) {
4419 rt2800_bbp_write(rt2x00dev, 105, 0x34);
4421 rt2800_bbp_write(rt2x00dev, 105, 0x04);
4425 reg = 0x2e + rt2x00dev->lna_gain;
4427 reg = 0x20 + ((rt2x00dev->lna_gain * 5) / 3);
4429 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4434 if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) {
4437 if (rt2x00_rt(rt2x00dev, RT6352) &&
4438 rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
4444 rt2800_bbp_write(rt2x00dev, 195, 141);
4445 rt2800_bbp_write(rt2x00dev, 196, reg);
4452 reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2*rt2x00dev->lna_gain;
4453 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
4455 if (rt2x00_rt(rt2x00dev, RT5592))
4456 rt2800_iq_calibrate(rt2x00dev, rf->channel);
4459 if (rt2x00_rt(rt2x00dev, RT6352)) {
4461 &rt2x00dev->cap_flags)) {
4462 reg = rt2800_register_read(rt2x00dev, RF_CONTROL3);
4464 rt2800_register_write(rt2x00dev, RF_CONTROL3, reg);
4466 reg = rt2800_register_read(rt2x00dev, RF_BYPASS3);
4468 rt2800_register_write(rt2x00dev, RF_BYPASS3, reg);
4470 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0x73);
4471 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0x73);
4472 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0x73);
4473 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
4474 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0xC8);
4475 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xA4);
4476 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x05);
4477 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
4478 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xC8);
4479 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xA4);
4480 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x05);
4481 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x27);
4482 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0xC8);
4483 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xA4);
4484 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x05);
4485 rt2800_rfcsr_write_dccal(rt2x00dev, 05, 0x00);
4487 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
4489 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN,
4491 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN,
4496 bbp = rt2800_bbp_read(rt2x00dev, 4);
4498 rt2800_bbp_write(rt2x00dev, 4, bbp);
4500 bbp = rt2800_bbp_read(rt2x00dev, 3);
4502 rt2800_bbp_write(rt2x00dev, 3, bbp);
4504 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
4506 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
4507 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
4508 rt2800_bbp_write(rt2x00dev, 73, 0x16);
4510 rt2800_bbp_write(rt2x00dev, 69, 0x16);
4511 rt2800_bbp_write(rt2x00dev, 70, 0x08);
4512 rt2800_bbp_write(rt2x00dev, 73, 0x11);
4521 reg = rt2800_register_read(rt2x00dev, CH_IDLE_STA);
4522 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA);
4523 reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC);
4528 if (rt2x00_rt(rt2x00dev, RT3352) ||
4529 rt2x00_rt(rt2x00dev, RT5350)) {
4530 bbp = rt2800_bbp_read(rt2x00dev, 49);
4532 rt2800_bbp_write(rt2x00dev, 49, bbp);
4536 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
4547 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
4559 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
4560 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1);
4566 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2);
4572 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3);
4578 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4);
4584 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5);
4591 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1);
4597 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2);
4603 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3);
4609 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4);
4615 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5);
4632 current_tssi = rt2800_bbp_read(rt2x00dev, 49);
4653 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
4661 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA);
4667 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4697 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
4702 if (rt2x00_has_cap_power_limit(rt2x00dev))
4718 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
4728 if (rt2x00_rt(rt2x00dev, RT3593))
4731 if (rt2x00_rt(rt2x00dev, RT3883))
4734 if (rt2x00_has_cap_power_limit(rt2x00dev)) {
4742 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
4748 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER);
4789 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
4806 delta = rt2800_get_gain_calibration_delta(rt2x00dev);
4813 if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4817 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4822 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
4833 txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
4844 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4855 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4865 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4870 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4881 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4892 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4902 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4907 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4918 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4929 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4940 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4950 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4955 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4966 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4977 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4988 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4998 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
5003 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5014 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5025 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5036 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5046 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
5051 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5062 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5073 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5083 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
5088 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5099 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5110 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5119 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5127 eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
5132 txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
5141 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
5142 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
5143 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
5144 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
5145 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
5146 rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
5147 rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
5148 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
5149 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
5150 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
5152 rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
5154 rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
5156 rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
5158 rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
5160 rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
5164 rt2x00_dbg(rt2x00dev,
5167 (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
5175 static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev,
5187 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
5190 rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n",
5208 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5226 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5243 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) {
5246 rt2800_register_write(rt2x00dev,
5252 rt2800_register_write(rt2x00dev,
5270 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_1);
5275 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_2);
5278 rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg);
5282 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_3);
5285 rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg);
5289 reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_4);
5292 rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg);
5294 rt2800_config_alc_rt6352(rt2x00dev, chan, power_level);
5308 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
5322 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
5331 switch (rt2x00dev->chip.rt) {
5339 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
5351 delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
5371 r1 = rt2800_bbp_read(rt2x00dev, 1);
5373 rt2800_bbp_write(rt2x00dev, 1, r1);
5382 reg = rt2800_register_read(rt2x00dev, offset);
5385 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5397 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5408 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5419 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5430 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5435 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
5447 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5458 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5469 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5480 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
5484 rt2800_register_write(rt2x00dev, offset, reg);
5491 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
5495 if (rt2x00_rt(rt2x00dev, RT3593) ||
5496 rt2x00_rt(rt2x00dev, RT3883))
5497 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
5498 else if (rt2x00_rt(rt2x00dev, RT6352))
5499 rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level);
5501 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
5504 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
5506 rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
5507 rt2x00dev->tx_power);
5511 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
5525 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
5527 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
5529 switch (rt2x00dev->chip.rf) {
5536 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
5538 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
5552 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
5554 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
5558 rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
5559 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
5560 rfcsr = rt2800_rfcsr_read(rt2x00dev, 4);
5562 rt2800_rfcsr_write(rt2x00dev, 4, rfcsr);
5567 rt2x00dev->chip.rf);
5574 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
5575 if (rt2x00dev->rf_channel <= 14) {
5576 switch (rt2x00dev->default_ant.tx_chain_num) {
5589 switch (rt2x00dev->default_ant.tx_chain_num) {
5602 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
5604 if (rt2x00_rt(rt2x00dev, RT6352)) {
5605 if (rt2x00dev->default_ant.rx_chain_num == 1) {
5606 rt2800_bbp_write(rt2x00dev, 91, 0x07);
5607 rt2800_bbp_write(rt2x00dev, 95, 0x1A);
5608 rt2800_bbp_write(rt2x00dev, 195, 128);
5609 rt2800_bbp_write(rt2x00dev, 196, 0xA0);
5610 rt2800_bbp_write(rt2x00dev, 195, 170);
5611 rt2800_bbp_write(rt2x00dev, 196, 0x12);
5612 rt2800_bbp_write(rt2x00dev, 195, 171);
5613 rt2800_bbp_write(rt2x00dev, 196, 0x10);
5615 rt2800_bbp_write(rt2x00dev, 91, 0x06);
5616 rt2800_bbp_write(rt2x00dev, 95, 0x9A);
5617 rt2800_bbp_write(rt2x00dev, 195, 128);
5618 rt2800_bbp_write(rt2x00dev, 196, 0xE0);
5619 rt2800_bbp_write(rt2x00dev, 195, 170);
5620 rt2800_bbp_write(rt2x00dev, 196, 0x30);
5621 rt2800_bbp_write(rt2x00dev, 195, 171);
5622 rt2800_bbp_write(rt2x00dev, 196, 0x30);
5625 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
5626 rt2800_bbp_write(rt2x00dev, 75, 0x68);
5627 rt2800_bbp_write(rt2x00dev, 76, 0x4C);
5628 rt2800_bbp_write(rt2x00dev, 79, 0x1C);
5629 rt2800_bbp_write(rt2x00dev, 80, 0x0C);
5630 rt2800_bbp_write(rt2x00dev, 82, 0xB6);
5643 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
5648 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG);
5653 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
5656 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
5665 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
5667 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG);
5672 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5674 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
5676 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG);
5680 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5682 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
5686 void rt2800_config(struct rt2x00_dev *rt2x00dev,
5691 rt2800_config_lna_gain(rt2x00dev, libconf);
5698 rt2800_update_survey(rt2x00dev);
5700 rt2800_config_channel(rt2x00dev, libconf->conf,
5702 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
5706 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
5709 rt2800_config_retry_limit(rt2x00dev, libconf);
5711 rt2800_config_ps(rt2x00dev, libconf);
5718 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
5725 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0);
5730 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
5734 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
5735 if (rt2x00_rt(rt2x00dev, RT3070) ||
5736 rt2x00_rt(rt2x00dev, RT3071) ||
5737 rt2x00_rt(rt2x00dev, RT3090) ||
5738 rt2x00_rt(rt2x00dev, RT3290) ||
5739 rt2x00_rt(rt2x00dev, RT3390) ||
5740 rt2x00_rt(rt2x00dev, RT3572) ||
5741 rt2x00_rt(rt2x00dev, RT3593) ||
5742 rt2x00_rt(rt2x00dev, RT5390) ||
5743 rt2x00_rt(rt2x00dev, RT5392) ||
5744 rt2x00_rt(rt2x00dev, RT5592) ||
5745 rt2x00_rt(rt2x00dev, RT6352))
5746 vgc = 0x1c + (2 * rt2x00dev->lna_gain);
5748 vgc = 0x2e + rt2x00dev->lna_gain;
5750 if (rt2x00_rt(rt2x00dev, RT3593) ||
5751 rt2x00_rt(rt2x00dev, RT3883))
5752 vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3;
5753 else if (rt2x00_rt(rt2x00dev, RT5592))
5754 vgc = 0x24 + (2 * rt2x00dev->lna_gain);
5756 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
5757 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
5759 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
5766 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
5770 if (rt2x00_rt(rt2x00dev, RT3572) ||
5771 rt2x00_rt(rt2x00dev, RT3593) ||
5772 rt2x00_rt(rt2x00dev, RT3883) ||
5773 rt2x00_rt(rt2x00dev, RT6352)) {
5774 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66,
5776 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
5777 rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
5778 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
5780 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
5788 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
5790 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
5794 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
5799 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
5807 vgc = rt2800_get_default_vgc(rt2x00dev);
5809 switch (rt2x00dev->chip.rt) {
5813 if (rt2x00dev->curr_band == NL80211_BAND_2GHZ)
5836 rt2800_set_vgc(rt2x00dev, qual, vgc);
5843 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
5845 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5851 rt2800_disable_wpdma(rt2x00dev);
5853 ret = rt2800_drv_init_registers(rt2x00dev);
5857 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
5858 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
5860 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
5862 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
5869 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
5871 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
5873 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG);
5876 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
5878 if (rt2x00_rt(rt2x00dev, RT3290)) {
5879 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
5882 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
5885 reg = rt2800_register_read(rt2x00dev, CMB_CTRL);
5889 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
5892 reg = rt2800_register_read(rt2x00dev, OSC_CTRL);
5896 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
5898 reg = rt2800_register_read(rt2x00dev, COEX_CFG0);
5900 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
5902 reg = rt2800_register_read(rt2x00dev, COEX_CFG2);
5907 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
5909 reg = rt2800_register_read(rt2x00dev, PLL_CTRL);
5911 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
5914 if (rt2x00_rt(rt2x00dev, RT3071) ||
5915 rt2x00_rt(rt2x00dev, RT3090) ||
5916 rt2x00_rt(rt2x00dev, RT3290) ||
5917 rt2x00_rt(rt2x00dev, RT3390)) {
5919 if (rt2x00_rt(rt2x00dev, RT3290))
5920 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
5923 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
5926 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5927 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5928 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5929 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
5930 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
5932 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5935 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5938 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5940 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
5941 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5943 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
5944 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5945 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
5947 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5948 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5950 } else if (rt2800_is_305x_soc(rt2x00dev)) {
5951 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5952 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5953 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
5954 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
5955 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5956 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5957 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5958 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
5959 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5960 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5961 } else if (rt2x00_rt(rt2x00dev, RT3593)) {
5962 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5963 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5964 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
5965 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
5968 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5971 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5974 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5977 } else if (rt2x00_rt(rt2x00dev, RT3883)) {
5978 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5979 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5980 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00040000);
5981 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_0, 0x8000fc21);
5982 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_3, 0x00009c40);
5983 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
5984 rt2x00_rt(rt2x00dev, RT5392)) {
5985 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5986 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5987 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5988 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
5989 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5990 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5991 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5992 } else if (rt2x00_rt(rt2x00dev, RT5350)) {
5993 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5994 } else if (rt2x00_rt(rt2x00dev, RT6352)) {
5995 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
5996 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0001);
5997 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5998 rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000);
5999 rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
6000 rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
6001 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);
6002 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);
6003 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
6005 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
6007 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
6009 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
6011 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
6012 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
6015 reg = rt2800_register_read(rt2x00dev, TX_LINK_CFG);
6024 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
6026 reg = rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG);
6030 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
6032 reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG);
6034 if (rt2x00_is_usb(rt2x00dev)) {
6036 } else if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
6037 rt2x00_rt(rt2x00dev, RT2883) ||
6038 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) {
6046 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
6048 reg = rt2800_register_read(rt2x00dev, LED_CFG);
6056 rt2800_register_write(rt2x00dev, LED_CFG, reg);
6058 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
6060 reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG);
6067 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
6069 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG);
6077 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
6079 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG);
6090 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
6092 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
6103 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
6105 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
6116 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
6118 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
6129 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
6131 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
6142 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
6144 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
6155 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
6157 if (rt2x00_is_usb(rt2x00dev)) {
6158 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
6160 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
6170 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
6177 reg = rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG);
6188 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
6190 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
6191 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
6193 if (rt2x00_rt(rt2x00dev, RT3883)) {
6194 rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_0, 0x12111008);
6195 rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_1, 0x16151413);
6198 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG);
6203 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
6205 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
6214 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG);
6220 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
6222 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
6228 rt2800_register_write(rt2x00dev, SHARED_KEY_MODE_ENTRY(i), 0);
6231 rt2800_config_wcid(rt2x00dev, NULL, i);
6232 rt2800_delete_wcid_attr(rt2x00dev, i);
6240 if (!test_bit(DEVICE_STATE_RESET, &rt2x00dev->flags))
6242 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
6248 rt2800_clear_beacon_register(rt2x00dev, i);
6250 if (rt2x00_is_usb(rt2x00dev)) {
6251 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
6253 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
6254 } else if (rt2x00_is_pcie(rt2x00dev)) {
6255 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
6257 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
6258 } else if (rt2x00_is_soc(rt2x00dev)) {
6276 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
6278 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
6281 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0);
6290 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
6292 reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG1);
6301 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
6303 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG0);
6312 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
6314 reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG1);
6319 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
6324 reg = rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE);
6327 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
6334 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0);
6335 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT1);
6336 reg = rt2800_register_read(rt2x00dev, RX_STA_CNT2);
6337 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT0);
6338 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT1);
6339 reg = rt2800_register_read(rt2x00dev, TX_STA_CNT2);
6344 reg = rt2800_register_read(rt2x00dev, INT_TIMER_CFG);
6346 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
6351 reg = rt2800_register_read(rt2x00dev, CH_TIME_CFG);
6357 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
6363 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
6367 value = rt2800_bbp_read(rt2x00dev, 4);
6369 rt2800_bbp_write(rt2x00dev, 4, value);
6372 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
6374 rt2800_bbp_write(rt2x00dev, 142, 1);
6375 rt2800_bbp_write(rt2x00dev, 143, 57);
6378 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
6394 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
6395 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
6399 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
6401 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6402 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6403 rt2800_bbp_write(rt2x00dev, 68, 0x0B);
6404 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6405 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6406 rt2800_bbp_write(rt2x00dev, 73, 0x10);
6407 rt2800_bbp_write(rt2x00dev, 81, 0x37);
6408 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6409 rt2800_bbp_write(rt2x00dev, 83, 0x6A);
6410 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6411 rt2800_bbp_write(rt2x00dev, 86, 0x00);
6412 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6413 rt2800_bbp_write(rt2x00dev, 92, 0x00);
6414 rt2800_bbp_write(rt2x00dev, 103, 0x00);
6415 rt2800_bbp_write(rt2x00dev, 105, 0x05);
6416 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6419 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
6424 value = rt2800_bbp_read(rt2x00dev, 138);
6425 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
6430 rt2800_bbp_write(rt2x00dev, 138, value);
6433 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
6435 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6437 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6438 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6440 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6441 rt2800_bbp_write(rt2x00dev, 73, 0x10);
6443 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6445 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
6446 rt2800_bbp_write(rt2x00dev, 80, 0x08);
6448 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6450 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6452 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6454 rt2800_bbp_write(rt2x00dev, 86, 0x00);
6456 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6458 rt2800_bbp_write(rt2x00dev, 92, 0x00);
6460 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6462 rt2800_bbp_write(rt2x00dev, 105, 0x01);
6464 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6467 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
6469 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6470 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6472 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
6473 rt2800_bbp_write(rt2x00dev, 69, 0x16);
6474 rt2800_bbp_write(rt2x00dev, 73, 0x12);
6476 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6477 rt2800_bbp_write(rt2x00dev, 73, 0x10);
6480 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6482 rt2800_bbp_write(rt2x00dev, 81, 0x37);
6484 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6486 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6488 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
6489 rt2800_bbp_write(rt2x00dev, 84, 0x19);
6491 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6493 rt2800_bbp_write(rt2x00dev, 86, 0x00);
6495 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6497 rt2800_bbp_write(rt2x00dev, 92, 0x00);
6499 rt2800_bbp_write(rt2x00dev, 103, 0x00);
6501 rt2800_bbp_write(rt2x00dev, 105, 0x05);
6503 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6506 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
6508 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6509 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6511 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6512 rt2800_bbp_write(rt2x00dev, 73, 0x10);
6514 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6516 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6517 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6518 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6520 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6522 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6524 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6526 rt2800_bbp_write(rt2x00dev, 86, 0x00);
6528 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6530 rt2800_bbp_write(rt2x00dev, 92, 0x00);
6532 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
6533 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
6534 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
6535 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6537 rt2800_bbp_write(rt2x00dev, 103, 0x00);
6539 rt2800_bbp_write(rt2x00dev, 105, 0x05);
6541 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6543 if (rt2x00_rt(rt2x00dev, RT3071) ||
6544 rt2x00_rt(rt2x00dev, RT3090))
6545 rt2800_disable_unused_dac_adc(rt2x00dev);
6548 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
6552 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6554 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6556 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6557 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6559 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6561 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6562 rt2800_bbp_write(rt2x00dev, 73, 0x13);
6563 rt2800_bbp_write(rt2x00dev, 75, 0x46);
6564 rt2800_bbp_write(rt2x00dev, 76, 0x28);
6566 rt2800_bbp_write(rt2x00dev, 77, 0x58);
6568 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6570 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
6571 rt2800_bbp_write(rt2x00dev, 79, 0x18);
6572 rt2800_bbp_write(rt2x00dev, 80, 0x09);
6573 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6575 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6577 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6579 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6581 rt2800_bbp_write(rt2x00dev, 86, 0x38);
6583 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6585 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6587 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6589 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6591 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
6593 rt2800_bbp_write(rt2x00dev, 106, 0x03);
6595 rt2800_bbp_write(rt2x00dev, 128, 0x12);
6597 rt2800_bbp_write(rt2x00dev, 67, 0x24);
6598 rt2800_bbp_write(rt2x00dev, 143, 0x04);
6599 rt2800_bbp_write(rt2x00dev, 142, 0x99);
6600 rt2800_bbp_write(rt2x00dev, 150, 0x30);
6601 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
6602 rt2800_bbp_write(rt2x00dev, 152, 0x20);
6603 rt2800_bbp_write(rt2x00dev, 153, 0x34);
6604 rt2800_bbp_write(rt2x00dev, 154, 0x40);
6605 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
6606 rt2800_bbp_write(rt2x00dev, 253, 0x04);
6608 value = rt2800_bbp_read(rt2x00dev, 47);
6610 rt2800_bbp_write(rt2x00dev, 47, value);
6613 value = rt2800_bbp_read(rt2x00dev, 3);
6616 rt2800_bbp_write(rt2x00dev, 3, value);
6619 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
6621 rt2800_bbp_write(rt2x00dev, 3, 0x00);
6622 rt2800_bbp_write(rt2x00dev, 4, 0x50);
6624 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6626 rt2800_bbp_write(rt2x00dev, 47, 0x48);
6628 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6629 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6631 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6633 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6634 rt2800_bbp_write(rt2x00dev, 73, 0x13);
6635 rt2800_bbp_write(rt2x00dev, 75, 0x46);
6636 rt2800_bbp_write(rt2x00dev, 76, 0x28);
6638 rt2800_bbp_write(rt2x00dev, 77, 0x59);
6640 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6642 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
6643 rt2800_bbp_write(rt2x00dev, 80, 0x08);
6644 rt2800_bbp_write(rt2x00dev, 81, 0x37);
6646 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6648 if (rt2x00_rt(rt2x00dev, RT5350)) {
6649 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6650 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6652 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6653 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6656 rt2800_bbp_write(rt2x00dev, 86, 0x38);
6658 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6660 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6662 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6664 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6666 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6668 if (rt2x00_rt(rt2x00dev, RT5350)) {
6669 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
6670 rt2800_bbp_write(rt2x00dev, 106, 0x03);
6672 rt2800_bbp_write(rt2x00dev, 105, 0x34);
6673 rt2800_bbp_write(rt2x00dev, 106, 0x05);
6676 rt2800_bbp_write(rt2x00dev, 120, 0x50);
6678 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6680 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
6682 rt2800_bbp_write(rt2x00dev, 179, 0x02);
6683 rt2800_bbp_write(rt2x00dev, 180, 0x00);
6684 rt2800_bbp_write(rt2x00dev, 182, 0x40);
6685 rt2800_bbp_write(rt2x00dev, 180, 0x01);
6686 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
6687 rt2800_bbp_write(rt2x00dev, 179, 0x00);
6689 rt2800_bbp_write(rt2x00dev, 142, 0x04);
6690 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
6691 rt2800_bbp_write(rt2x00dev, 142, 0x06);
6692 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
6693 rt2800_bbp_write(rt2x00dev, 142, 0x07);
6694 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
6695 rt2800_bbp_write(rt2x00dev, 142, 0x08);
6696 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
6698 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6700 if (rt2x00_rt(rt2x00dev, RT5350)) {
6702 rt2800_bbp_write(rt2x00dev, 150, 0x40);
6704 rt2800_bbp_write(rt2x00dev, 151, 0x30);
6705 rt2800_bbp_write(rt2x00dev, 152, 0xa3);
6707 rt2800_bbp_write(rt2x00dev, 154, 0);
6711 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
6713 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6714 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6716 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6717 rt2800_bbp_write(rt2x00dev, 73, 0x10);
6719 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6721 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6722 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6723 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6725 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6727 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6729 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6731 rt2800_bbp_write(rt2x00dev, 86, 0x00);
6733 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6735 rt2800_bbp_write(rt2x00dev, 92, 0x00);
6737 if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
6738 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6740 rt2800_bbp_write(rt2x00dev, 103, 0x00);
6742 rt2800_bbp_write(rt2x00dev, 105, 0x05);
6744 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6746 rt2800_disable_unused_dac_adc(rt2x00dev);
6749 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
6751 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6753 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6754 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6756 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6757 rt2800_bbp_write(rt2x00dev, 73, 0x10);
6759 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6761 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6762 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6763 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6765 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6767 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6769 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6771 rt2800_bbp_write(rt2x00dev, 86, 0x00);
6773 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6775 rt2800_bbp_write(rt2x00dev, 92, 0x00);
6777 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6779 rt2800_bbp_write(rt2x00dev, 105, 0x05);
6781 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6783 rt2800_disable_unused_dac_adc(rt2x00dev);
6786 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
6788 rt2800_init_bbp_early(rt2x00dev);
6790 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6791 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6792 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6793 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6795 rt2800_bbp_write(rt2x00dev, 84, 0x19);
6798 if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
6799 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6802 static void rt2800_init_bbp_3883(struct rt2x00_dev *rt2x00dev)
6804 rt2800_init_bbp_early(rt2x00dev);
6806 rt2800_bbp_write(rt2x00dev, 4, 0x50);
6807 rt2800_bbp_write(rt2x00dev, 47, 0x48);
6809 rt2800_bbp_write(rt2x00dev, 86, 0x46);
6810 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6812 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6814 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6815 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6816 rt2800_bbp_write(rt2x00dev, 105, 0x34);
6817 rt2800_bbp_write(rt2x00dev, 106, 0x12);
6818 rt2800_bbp_write(rt2x00dev, 120, 0x50);
6819 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6820 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
6823 rt2800_bbp_write(rt2x00dev, 179, 0x02);
6824 rt2800_bbp_write(rt2x00dev, 180, 0x00);
6825 rt2800_bbp_write(rt2x00dev, 182, 0x40);
6826 rt2800_bbp_write(rt2x00dev, 180, 0x01);
6827 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
6829 rt2800_bbp_write(rt2x00dev, 179, 0x00);
6832 rt2800_bbp_write(rt2x00dev, 142, 0x04);
6833 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
6834 rt2800_bbp_write(rt2x00dev, 142, 0x06);
6835 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
6836 rt2800_bbp_write(rt2x00dev, 142, 0x07);
6837 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
6838 rt2800_bbp_write(rt2x00dev, 142, 0x08);
6839 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
6840 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6843 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
6849 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6851 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6853 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6854 rt2800_bbp_write(rt2x00dev, 66, 0x38);
6856 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6858 rt2800_bbp_write(rt2x00dev, 69, 0x12);
6859 rt2800_bbp_write(rt2x00dev, 73, 0x13);
6860 rt2800_bbp_write(rt2x00dev, 75, 0x46);
6861 rt2800_bbp_write(rt2x00dev, 76, 0x28);
6863 rt2800_bbp_write(rt2x00dev, 77, 0x59);
6865 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6867 rt2800_bbp_write(rt2x00dev, 79, 0x13);
6868 rt2800_bbp_write(rt2x00dev, 80, 0x05);
6869 rt2800_bbp_write(rt2x00dev, 81, 0x33);
6871 rt2800_bbp_write(rt2x00dev, 82, 0x62);
6873 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6875 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6877 rt2800_bbp_write(rt2x00dev, 86, 0x38);
6879 if (rt2x00_rt(rt2x00dev, RT5392))
6880 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6882 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6884 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6886 if (rt2x00_rt(rt2x00dev, RT5392)) {
6887 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
6888 rt2800_bbp_write(rt2x00dev, 98, 0x12);
6891 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6893 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6895 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
6897 if (rt2x00_rt(rt2x00dev, RT5390))
6898 rt2800_bbp_write(rt2x00dev, 106, 0x03);
6899 else if (rt2x00_rt(rt2x00dev, RT5392))
6900 rt2800_bbp_write(rt2x00dev, 106, 0x12);
6904 rt2800_bbp_write(rt2x00dev, 128, 0x12);
6906 if (rt2x00_rt(rt2x00dev, RT5392)) {
6907 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
6908 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
6911 rt2800_disable_unused_dac_adc(rt2x00dev);
6913 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
6919 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
6922 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
6931 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
6935 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) ||
6936 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) {
6937 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
6938 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
6939 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
6942 value = rt2800_bbp_read(rt2x00dev, 152);
6947 rt2800_bbp_write(rt2x00dev, 152, value);
6949 rt2800_init_freq_calibration(rt2x00dev);
6952 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
6958 rt2800_init_bbp_early(rt2x00dev);
6960 value = rt2800_bbp_read(rt2x00dev, 105);
6962 rt2x00dev->default_ant.rx_chain_num == 2);
6963 rt2800_bbp_write(rt2x00dev, 105, value);
6965 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6967 rt2800_bbp_write(rt2x00dev, 20, 0x06);
6968 rt2800_bbp_write(rt2x00dev, 31, 0x08);
6969 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6970 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
6971 rt2800_bbp_write(rt2x00dev, 69, 0x1A);
6972 rt2800_bbp_write(rt2x00dev, 70, 0x05);
6973 rt2800_bbp_write(rt2x00dev, 73, 0x13);
6974 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
6975 rt2800_bbp_write(rt2x00dev, 75, 0x4F);
6976 rt2800_bbp_write(rt2x00dev, 76, 0x28);
6977 rt2800_bbp_write(rt2x00dev, 77, 0x59);
6978 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
6979 rt2800_bbp_write(rt2x00dev, 86, 0x38);
6980 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6981 rt2800_bbp_write(rt2x00dev, 91, 0x04);
6982 rt2800_bbp_write(rt2x00dev, 92, 0x02);
6983 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
6984 rt2800_bbp_write(rt2x00dev, 98, 0x12);
6985 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
6986 rt2800_bbp_write(rt2x00dev, 104, 0x92);
6988 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
6989 rt2800_bbp_write(rt2x00dev, 106, 0x35);
6990 rt2800_bbp_write(rt2x00dev, 128, 0x12);
6991 rt2800_bbp_write(rt2x00dev, 134, 0xD0);
6992 rt2800_bbp_write(rt2x00dev, 135, 0xF6);
6993 rt2800_bbp_write(rt2x00dev, 137, 0x0F);
6996 rt2800_init_bbp_5592_glrt(rt2x00dev);
6998 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7000 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
7003 value = rt2800_bbp_read(rt2x00dev, 152);
7011 rt2800_bbp_write(rt2x00dev, 152, value);
7013 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
7014 value = rt2800_bbp_read(rt2x00dev, 254);
7016 rt2800_bbp_write(rt2x00dev, 254, value);
7019 rt2800_init_freq_calibration(rt2x00dev);
7021 rt2800_bbp_write(rt2x00dev, 84, 0x19);
7022 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
7023 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
7026 static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev)
7031 bbp = rt2800_bbp_read(rt2x00dev, 105);
7033 rt2x00dev->default_ant.rx_chain_num == 2);
7034 rt2800_bbp_write(rt2x00dev, 105, bbp);
7037 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7040 bbp = rt2800_bbp_read(rt2x00dev, 1);
7042 rt2800_bbp_write(rt2x00dev, 1, bbp);
7045 rt2800_bbp_write(rt2x00dev, 3, 0x08);
7046 rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */
7047 rt2800_bbp_write(rt2x00dev, 6, 0x08);
7048 rt2800_bbp_write(rt2x00dev, 14, 0x09);
7049 rt2800_bbp_write(rt2x00dev, 15, 0xFF);
7050 rt2800_bbp_write(rt2x00dev, 16, 0x01);
7051 rt2800_bbp_write(rt2x00dev, 20, 0x06);
7052 rt2800_bbp_write(rt2x00dev, 21, 0x00);
7053 rt2800_bbp_write(rt2x00dev, 22, 0x00);
7054 rt2800_bbp_write(rt2x00dev, 27, 0x00);
7055 rt2800_bbp_write(rt2x00dev, 28, 0x00);
7056 rt2800_bbp_write(rt2x00dev, 30, 0x00);
7057 rt2800_bbp_write(rt2x00dev, 31, 0x48);
7058 rt2800_bbp_write(rt2x00dev, 47, 0x40);
7059 rt2800_bbp_write(rt2x00dev, 62, 0x00);
7060 rt2800_bbp_write(rt2x00dev, 63, 0x00);
7061 rt2800_bbp_write(rt2x00dev, 64, 0x00);
7062 rt2800_bbp_write(rt2x00dev, 65, 0x2C);
7063 rt2800_bbp_write(rt2x00dev, 66, 0x1C);
7064 rt2800_bbp_write(rt2x00dev, 67, 0x20);
7065 rt2800_bbp_write(rt2x00dev, 68, 0xDD);
7066 rt2800_bbp_write(rt2x00dev, 69, 0x10);
7067 rt2800_bbp_write(rt2x00dev, 70, 0x05);
7068 rt2800_bbp_write(rt2x00dev, 73, 0x18);
7069 rt2800_bbp_write(rt2x00dev, 74, 0x0F);
7070 rt2800_bbp_write(rt2x00dev, 75, 0x60);
7071 rt2800_bbp_write(rt2x00dev, 76, 0x44);
7072 rt2800_bbp_write(rt2x00dev, 77, 0x59);
7073 rt2800_bbp_write(rt2x00dev, 78, 0x1E);
7074 rt2800_bbp_write(rt2x00dev, 79, 0x1C);
7075 rt2800_bbp_write(rt2x00dev, 80, 0x0C);
7076 rt2800_bbp_write(rt2x00dev, 81, 0x3A);
7077 rt2800_bbp_write(rt2x00dev, 82, 0xB6);
7078 rt2800_bbp_write(rt2x00dev, 83, 0x9A);
7079 rt2800_bbp_write(rt2x00dev, 84, 0x9A);
7080 rt2800_bbp_write(rt2x00dev, 86, 0x38);
7081 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7082 rt2800_bbp_write(rt2x00dev, 91, 0x04);
7083 rt2800_bbp_write(rt2x00dev, 92, 0x02);
7084 rt2800_bbp_write(rt2x00dev, 95, 0x9A);
7085 rt2800_bbp_write(rt2x00dev, 96, 0x00);
7086 rt2800_bbp_write(rt2x00dev, 103, 0xC0);
7087 rt2800_bbp_write(rt2x00dev, 104, 0x92);
7089 rt2800_bbp_write(rt2x00dev, 105, 0x3C);
7090 rt2800_bbp_write(rt2x00dev, 106, 0x12);
7091 rt2800_bbp_write(rt2x00dev, 109, 0x00);
7092 rt2800_bbp_write(rt2x00dev, 134, 0x10);
7093 rt2800_bbp_write(rt2x00dev, 135, 0xA6);
7094 rt2800_bbp_write(rt2x00dev, 137, 0x04);
7095 rt2800_bbp_write(rt2x00dev, 142, 0x30);
7096 rt2800_bbp_write(rt2x00dev, 143, 0xF7);
7097 rt2800_bbp_write(rt2x00dev, 160, 0xEC);
7098 rt2800_bbp_write(rt2x00dev, 161, 0xC4);
7099 rt2800_bbp_write(rt2x00dev, 162, 0x77);
7100 rt2800_bbp_write(rt2x00dev, 163, 0xF9);
7101 rt2800_bbp_write(rt2x00dev, 164, 0x00);
7102 rt2800_bbp_write(rt2x00dev, 165, 0x00);
7103 rt2800_bbp_write(rt2x00dev, 186, 0x00);
7104 rt2800_bbp_write(rt2x00dev, 187, 0x00);
7105 rt2800_bbp_write(rt2x00dev, 188, 0x00);
7106 rt2800_bbp_write(rt2x00dev, 186, 0x00);
7107 rt2800_bbp_write(rt2x00dev, 187, 0x01);
7108 rt2800_bbp_write(rt2x00dev, 188, 0x00);
7109 rt2800_bbp_write(rt2x00dev, 189, 0x00);
7111 rt2800_bbp_write(rt2x00dev, 91, 0x06);
7112 rt2800_bbp_write(rt2x00dev, 92, 0x04);
7113 rt2800_bbp_write(rt2x00dev, 93, 0x54);
7114 rt2800_bbp_write(rt2x00dev, 99, 0x50);
7115 rt2800_bbp_write(rt2x00dev, 148, 0x84);
7116 rt2800_bbp_write(rt2x00dev, 167, 0x80);
7117 rt2800_bbp_write(rt2x00dev, 178, 0xFF);
7118 rt2800_bbp_write(rt2x00dev, 106, 0x13);
7121 rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);
7122 rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14);
7123 rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20);
7124 rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A);
7125 rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16);
7126 rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06);
7127 rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02);
7128 rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07);
7129 rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05);
7130 rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09);
7131 rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20);
7132 rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08);
7133 rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A);
7134 rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00);
7135 rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00);
7136 rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0);
7137 rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F);
7138 rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F);
7139 rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32);
7140 rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08);
7141 rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28);
7142 rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19);
7143 rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A);
7144 rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16);
7145 rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10);
7146 rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10);
7147 rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A);
7148 rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36);
7149 rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C);
7150 rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26);
7151 rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24);
7152 rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42);
7153 rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40);
7154 rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30);
7155 rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29);
7156 rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C);
7157 rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46);
7158 rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D);
7159 rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40);
7160 rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E);
7161 rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38);
7162 rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D);
7163 rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F);
7164 rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C);
7165 rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34);
7166 rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C);
7167 rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F);
7168 rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C);
7169 rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35);
7170 rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E);
7171 rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F);
7172 rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49);
7173 rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41);
7174 rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36);
7175 rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39);
7176 rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30);
7177 rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30);
7178 rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E);
7179 rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D);
7180 rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28);
7181 rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21);
7182 rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C);
7183 rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16);
7184 rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50);
7185 rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A);
7186 rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43);
7187 rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50);
7188 rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10);
7189 rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10);
7190 rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10);
7191 rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10);
7192 rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D);
7193 rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14);
7194 rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32);
7195 rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C);
7196 rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36);
7197 rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C);
7198 rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43);
7199 rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C);
7200 rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E);
7201 rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36);
7202 rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30);
7203 rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E);
7206 rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C);
7207 rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00);
7208 rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10);
7209 rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10);
7210 rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10);
7211 rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10);
7212 rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08);
7213 rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40);
7214 rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04);
7215 rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04);
7216 rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08);
7217 rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08);
7218 rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03);
7219 rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03);
7220 rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03);
7221 rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02);
7222 rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40);
7223 rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40);
7224 rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64);
7225 rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64);
7227 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7230 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
7237 if (rt2800_is_305x_soc(rt2x00dev))
7238 rt2800_init_bbp_305x_soc(rt2x00dev);
7240 switch (rt2x00dev->chip.rt) {
7244 rt2800_init_bbp_28xx(rt2x00dev);
7249 rt2800_init_bbp_30xx(rt2x00dev);
7252 rt2800_init_bbp_3290(rt2x00dev);
7256 rt2800_init_bbp_3352(rt2x00dev);
7259 rt2800_init_bbp_3390(rt2x00dev);
7262 rt2800_init_bbp_3572(rt2x00dev);
7265 rt2800_init_bbp_3593(rt2x00dev);
7268 rt2800_init_bbp_3883(rt2x00dev);
7272 rt2800_init_bbp_53xx(rt2x00dev);
7275 rt2800_init_bbp_5592(rt2x00dev);
7278 rt2800_init_bbp_6352(rt2x00dev);
7283 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
7289 rt2800_bbp_write(rt2x00dev, reg_id, value);
7294 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
7298 reg = rt2800_register_read(rt2x00dev, OPT_14_CSR);
7300 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
7303 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
7314 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
7316 bbp = rt2800_bbp_read(rt2x00dev, 4);
7318 rt2800_bbp_write(rt2x00dev, 4, bbp);
7320 rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
7322 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
7324 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
7326 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
7331 rt2800_bbp_write(rt2x00dev, 24, 0);
7334 rt2800_bbp_write(rt2x00dev, 25, 0x90);
7337 passband = rt2800_bbp_read(rt2x00dev, 55);
7345 rt2800_bbp_write(rt2x00dev, 24, 0x06);
7348 rt2800_bbp_write(rt2x00dev, 25, 0x90);
7351 stopband = rt2800_bbp_read(rt2x00dev, 55);
7359 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
7364 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
7368 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
7373 rfcsr = rt2800_rfcsr_read(rt2x00dev, rf_reg);
7375 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
7378 rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
7381 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
7383 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7391 if (rt2x00_rt(rt2x00dev, RT3070)) {
7400 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
7402 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
7407 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25);
7408 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26);
7413 rt2800_bbp_write(rt2x00dev, 24, 0);
7415 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
7417 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
7422 bbp = rt2800_bbp_read(rt2x00dev, 4);
7424 rt2800_bbp_write(rt2x00dev, 4, bbp);
7427 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
7429 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7433 rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
7436 if (rt2x00_rt(rt2x00dev, RT3070) ||
7437 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
7438 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
7439 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
7440 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev))
7444 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
7450 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
7452 if (rt2x00_rt(rt2x00dev, RT3090)) {
7454 bbp = rt2800_bbp_read(rt2x00dev, 138);
7455 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
7460 rt2800_bbp_write(rt2x00dev, 138, bbp);
7463 if (rt2x00_rt(rt2x00dev, RT3070)) {
7464 rfcsr = rt2800_rfcsr_read(rt2x00dev, 27);
7465 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
7472 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
7473 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
7474 rt2x00_rt(rt2x00dev, RT3090) ||
7475 rt2x00_rt(rt2x00dev, RT3390)) {
7476 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
7482 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
7484 rfcsr = rt2800_rfcsr_read(rt2x00dev, 15);
7486 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
7488 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
7490 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
7492 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
7494 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
7498 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
7500 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7504 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
7506 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
7508 rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
7512 rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
7514 rfcsr = rt2800_rfcsr_read(rt2x00dev, 38);
7516 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
7518 rfcsr = rt2800_rfcsr_read(rt2x00dev, 39);
7520 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
7522 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
7525 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
7527 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
7529 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
7534 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
7540 reg = rt2800_bbp_read(rt2x00dev, 138);
7541 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
7546 rt2800_bbp_write(rt2x00dev, 138, reg);
7548 reg = rt2800_rfcsr_read(rt2x00dev, 38);
7550 rt2800_rfcsr_write(rt2x00dev, 38, reg);
7552 reg = rt2800_rfcsr_read(rt2x00dev, 39);
7554 rt2800_rfcsr_write(rt2x00dev, 39, reg);
7556 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7558 reg = rt2800_rfcsr_read(rt2x00dev, 30);
7560 rt2800_rfcsr_write(rt2x00dev, 30, reg);
7563 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
7565 rt2800_rf_init_calibration(rt2x00dev, 30);
7567 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
7568 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
7569 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
7570 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
7571 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7572 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
7573 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
7574 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
7575 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
7576 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
7577 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
7578 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7579 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
7580 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
7581 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7582 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
7583 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
7584 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
7585 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
7586 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7587 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
7588 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
7589 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7590 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
7591 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
7592 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
7593 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
7594 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
7595 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
7596 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
7597 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
7598 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
7601 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
7608 rt2800_rf_init_calibration(rt2x00dev, 30);
7610 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7611 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
7612 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
7613 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
7614 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
7615 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
7616 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7617 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
7618 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7619 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
7620 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
7621 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
7622 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
7623 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7624 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
7625 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
7626 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
7627 rt2800_rfcsr_write(rt2x00dev, 25, 0x03);
7628 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
7630 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
7631 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7634 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7635 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
7636 rt2x00_rt(rt2x00dev, RT3090)) {
7637 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
7639 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
7641 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
7643 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7645 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
7646 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
7647 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
7653 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7655 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7657 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7660 rt2800_rx_filter_calibration(rt2x00dev);
7662 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
7663 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
7664 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
7665 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7667 rt2800_led_open_drain_enable(rt2x00dev);
7668 rt2800_normal_mode_setup_3xxx(rt2x00dev);
7671 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
7675 rt2800_rf_init_calibration(rt2x00dev, 2);
7677 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
7678 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
7679 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
7680 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
7681 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
7682 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
7683 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7684 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7685 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7686 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7687 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7688 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
7689 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7690 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
7691 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
7692 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
7693 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
7694 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7695 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7696 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7697 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7698 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
7699 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7700 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7701 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
7702 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7703 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
7704 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7705 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
7706 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
7707 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
7708 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
7709 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7710 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
7711 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7712 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
7713 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
7714 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
7715 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
7716 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
7717 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
7718 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
7719 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
7720 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
7721 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7722 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
7724 rfcsr = rt2800_rfcsr_read(rt2x00dev, 29);
7726 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
7728 rt2800_led_open_drain_enable(rt2x00dev);
7729 rt2800_normal_mode_setup_3xxx(rt2x00dev);
7732 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
7735 &rt2x00dev->cap_flags);
7737 &rt2x00dev->cap_flags);
7740 rt2800_rf_init_calibration(rt2x00dev, 30);
7742 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
7743 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
7744 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
7745 rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
7746 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
7747 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
7748 rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
7749 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7750 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7751 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7752 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
7753 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
7754 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
7755 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
7756 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
7757 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7758 rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
7759 rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
7760 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7761 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7762 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
7763 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7764 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
7765 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
7766 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7767 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
7768 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7769 rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
7770 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
7771 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7772 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7773 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7774 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7780 rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
7781 rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
7782 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
7783 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
7784 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
7785 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
7786 rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
7792 rt2800_rfcsr_write(rt2x00dev, 41, rfcsr);
7798 rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
7799 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
7800 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
7801 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
7802 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
7803 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
7804 rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
7805 rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
7811 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
7812 rt2800_rfcsr_write(rt2x00dev, 51, (tx0_ext_pa ? 0x52 : 0x7f));
7813 rt2800_rfcsr_write(rt2x00dev, 52, (tx0_ext_pa ? 0xc0 : 0x00));
7814 rt2800_rfcsr_write(rt2x00dev, 53, (tx0_ext_pa ? 0xd2 : 0x52));
7815 rt2800_rfcsr_write(rt2x00dev, 54, (tx0_ext_pa ? 0xc0 : 0x1b));
7816 rt2800_rfcsr_write(rt2x00dev, 55, (tx1_ext_pa ? 0x52 : 0x7f));
7817 rt2800_rfcsr_write(rt2x00dev, 56, (tx1_ext_pa ? 0xc0 : 0x00));
7818 rt2800_rfcsr_write(rt2x00dev, 57, (tx0_ext_pa ? 0x49 : 0x52));
7819 rt2800_rfcsr_write(rt2x00dev, 58, (tx1_ext_pa ? 0xc0 : 0x1b));
7820 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
7821 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
7822 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
7823 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
7824 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
7826 rt2800_rx_filter_calibration(rt2x00dev);
7827 rt2800_led_open_drain_enable(rt2x00dev);
7828 rt2800_normal_mode_setup_3xxx(rt2x00dev);
7831 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
7835 rt2800_rf_init_calibration(rt2x00dev, 30);
7837 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
7838 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
7839 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
7840 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
7841 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7842 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
7843 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
7844 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
7845 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
7846 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
7847 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
7848 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7849 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
7850 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
7851 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7852 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
7853 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
7854 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
7855 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
7856 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
7857 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
7858 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
7859 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7860 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
7861 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
7862 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
7863 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
7864 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
7865 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
7866 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
7867 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
7868 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
7870 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7872 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7874 rt2800_rx_filter_calibration(rt2x00dev);
7876 if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
7877 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7879 rt2800_led_open_drain_enable(rt2x00dev);
7880 rt2800_normal_mode_setup_3xxx(rt2x00dev);
7883 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
7888 rt2800_rf_init_calibration(rt2x00dev, 30);
7890 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
7891 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
7892 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
7893 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
7894 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
7895 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
7896 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
7897 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
7898 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
7899 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
7900 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
7901 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
7902 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
7903 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
7904 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
7905 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
7906 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
7907 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
7908 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
7909 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
7910 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
7911 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7912 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
7913 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
7914 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
7915 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
7916 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
7917 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7918 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
7919 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
7920 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
7922 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
7924 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
7926 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7929 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7931 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7934 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7936 rt2800_rx_filter_calibration(rt2x00dev);
7937 rt2800_led_open_drain_enable(rt2x00dev);
7938 rt2800_normal_mode_setup_3xxx(rt2x00dev);
7941 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
7946 bbp = rt2800_bbp_read(rt2x00dev, 105);
7947 if (rt2x00dev->default_ant.rx_chain_num == 1)
7951 rt2800_bbp_write(rt2x00dev, 105, bbp);
7953 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7955 rt2800_bbp_write(rt2x00dev, 92, 0x02);
7956 rt2800_bbp_write(rt2x00dev, 82, 0x82);
7957 rt2800_bbp_write(rt2x00dev, 106, 0x05);
7958 rt2800_bbp_write(rt2x00dev, 104, 0x92);
7959 rt2800_bbp_write(rt2x00dev, 88, 0x90);
7960 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
7961 rt2800_bbp_write(rt2x00dev, 47, 0x48);
7962 rt2800_bbp_write(rt2x00dev, 120, 0x50);
7965 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
7967 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
7970 rt2800_bbp_write(rt2x00dev, 142, 6);
7971 rt2800_bbp_write(rt2x00dev, 143, 160);
7972 rt2800_bbp_write(rt2x00dev, 142, 7);
7973 rt2800_bbp_write(rt2x00dev, 143, 161);
7974 rt2800_bbp_write(rt2x00dev, 142, 8);
7975 rt2800_bbp_write(rt2x00dev, 143, 162);
7978 rt2800_bbp_write(rt2x00dev, 31, 0x08);
7981 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
7984 rt2800_bbp_write(rt2x00dev, 105, 0x04);
7988 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
7990 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7995 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7998 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
8001 rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
8002 rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
8003 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
8004 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
8005 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
8006 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
8007 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
8008 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
8009 rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
8010 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
8011 rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
8012 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8013 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8014 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8015 rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
8016 rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
8017 rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
8018 rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
8019 rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
8020 rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
8021 rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
8022 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
8023 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
8024 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
8025 rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
8026 rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
8027 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
8028 rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
8029 rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
8030 rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
8031 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
8032 rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
8036 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
8038 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
8040 rt2800_freq_cal_mode1(rt2x00dev);
8042 rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
8044 rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
8046 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
8049 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
8051 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
8053 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
8060 drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25);
8061 drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26);
8063 rt2800_led_open_drain_enable(rt2x00dev);
8064 rt2800_normal_mode_setup_3593(rt2x00dev);
8066 rt3593_post_bbp_init(rt2x00dev);
8071 static void rt2800_init_rfcsr_5350(struct rt2x00_dev *rt2x00dev)
8073 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
8074 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
8075 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
8076 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
8077 rt2800_rfcsr_write(rt2x00dev, 4, 0x49);
8078 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8079 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
8080 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8081 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
8082 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
8083 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
8084 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
8085 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
8086 if (rt2800_clk_is_20mhz(rt2x00dev))
8087 rt2800_rfcsr_write(rt2x00dev, 13, 0x1f);
8089 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
8090 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8091 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8092 rt2800_rfcsr_write(rt2x00dev, 16, 0xc0);
8093 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8094 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8095 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8096 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
8097 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8098 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
8099 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8100 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
8101 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
8102 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
8103 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8104 rt2800_rfcsr_write(rt2x00dev, 29, 0xd0);
8105 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8106 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8107 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
8108 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8109 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8110 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8111 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8112 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
8113 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
8114 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
8115 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
8116 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
8117 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
8118 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
8119 rt2800_rfcsr_write(rt2x00dev, 44, 0x0c);
8120 rt2800_rfcsr_write(rt2x00dev, 45, 0xa6);
8121 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
8122 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
8123 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
8124 rt2800_rfcsr_write(rt2x00dev, 49, 0x80);
8125 rt2800_rfcsr_write(rt2x00dev, 50, 0x00);
8126 rt2800_rfcsr_write(rt2x00dev, 51, 0x00);
8127 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
8128 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
8129 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
8130 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
8131 rt2800_rfcsr_write(rt2x00dev, 56, 0x82);
8132 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
8133 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
8134 rt2800_rfcsr_write(rt2x00dev, 59, 0x0b);
8135 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
8136 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
8137 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
8138 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8141 static void rt2800_init_rfcsr_3883(struct rt2x00_dev *rt2x00dev)
8148 rt2800_rf_init_calibration(rt2x00dev, 2);
8150 rt2800_rfcsr_write(rt2x00dev, 0, 0xe0);
8151 rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
8152 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
8153 rt2800_rfcsr_write(rt2x00dev, 3, 0x20);
8154 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
8155 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
8156 rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
8157 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8158 rt2800_rfcsr_write(rt2x00dev, 8, 0x5b);
8159 rt2800_rfcsr_write(rt2x00dev, 9, 0x08);
8160 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
8161 rt2800_rfcsr_write(rt2x00dev, 11, 0x48);
8162 rt2800_rfcsr_write(rt2x00dev, 12, 0x1a);
8163 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
8164 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8165 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8166 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8172 rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
8173 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8174 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8175 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
8176 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8177 rt2800_rfcsr_write(rt2x00dev, 23, 0xc0);
8178 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8179 rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
8180 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
8181 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8182 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8183 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
8184 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8185 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8186 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
8187 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8188 rt2800_rfcsr_write(rt2x00dev, 34, 0x20);
8189 rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
8190 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8191 rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
8192 rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
8193 rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
8194 rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
8195 rt2800_rfcsr_write(rt2x00dev, 41, 0x00);
8196 rt2800_rfcsr_write(rt2x00dev, 42, 0x00);
8197 rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
8198 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
8199 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
8200 rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
8201 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
8202 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
8203 rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
8204 rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
8205 rt2800_rfcsr_write(rt2x00dev, 51, 0x51);
8206 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
8207 rt2800_rfcsr_write(rt2x00dev, 53, 0x76);
8208 rt2800_rfcsr_write(rt2x00dev, 54, 0x76);
8209 rt2800_rfcsr_write(rt2x00dev, 55, 0x76);
8210 rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
8211 rt2800_rfcsr_write(rt2x00dev, 57, 0x3e);
8212 rt2800_rfcsr_write(rt2x00dev, 58, 0x00);
8213 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
8214 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
8215 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
8216 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
8217 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8221 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
8223 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
8225 rt2800_bbp_write(rt2x00dev, 105, 0x05);
8227 rt2800_bbp_write(rt2x00dev, 179, 0x02);
8228 rt2800_bbp_write(rt2x00dev, 180, 0x00);
8229 rt2800_bbp_write(rt2x00dev, 182, 0x40);
8230 rt2800_bbp_write(rt2x00dev, 180, 0x01);
8231 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
8233 rt2800_bbp_write(rt2x00dev, 179, 0x00);
8235 rt2800_bbp_write(rt2x00dev, 142, 0x04);
8236 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
8237 rt2800_bbp_write(rt2x00dev, 142, 0x06);
8238 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
8239 rt2800_bbp_write(rt2x00dev, 142, 0x07);
8240 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
8241 rt2800_bbp_write(rt2x00dev, 142, 0x08);
8242 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
8243 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
8246 rt2800_rfcsr_write(rt2x00dev, 32, 0xd8);
8247 rt2800_rfcsr_write(rt2x00dev, 33, 0x32);
8250 rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
8253 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
8256 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
8258 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
8260 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
8262 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
8264 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
8266 rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
8268 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
8270 rfcsr = rt2800_rfcsr_read(rt2x00dev, 46);
8272 rt2800_rfcsr_write(rt2x00dev, 46, rfcsr);
8274 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
8276 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
8279 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
8281 rt2800_rf_init_calibration(rt2x00dev, 2);
8283 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
8284 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
8285 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
8286 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8287 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8288 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
8290 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
8291 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8292 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
8293 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
8294 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
8295 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
8296 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8297 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8298 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8299 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8300 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8302 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8303 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
8304 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8305 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
8306 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8307 if (rt2x00_is_usb(rt2x00dev) &&
8308 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8309 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
8311 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
8312 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
8313 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
8314 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8315 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
8317 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8318 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8319 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
8320 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8321 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8322 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8323 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8324 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
8325 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
8326 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
8328 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
8329 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
8330 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
8331 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
8332 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
8333 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
8334 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8335 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
8337 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
8338 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
8339 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
8340 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
8342 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
8343 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8344 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
8346 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
8347 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
8348 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
8349 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
8350 rt2800_rfcsr_write(rt2x00dev, 56, 0x42);
8352 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
8353 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
8354 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
8355 rt2800_rfcsr_write(rt2x00dev, 59, 0x8f);
8357 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
8358 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
8359 if (rt2x00_is_usb(rt2x00dev))
8360 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
8362 rt2800_rfcsr_write(rt2x00dev, 61, 0xd5);
8364 if (rt2x00_is_usb(rt2x00dev))
8365 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
8367 rt2800_rfcsr_write(rt2x00dev, 61, 0xb5);
8369 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
8370 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
8372 rt2800_normal_mode_setup_5xxx(rt2x00dev);
8374 rt2800_led_open_drain_enable(rt2x00dev);
8377 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
8379 rt2800_rf_init_calibration(rt2x00dev, 2);
8381 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
8382 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
8383 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8384 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
8385 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8386 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
8387 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
8388 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
8389 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
8390 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8391 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8392 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8393 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8394 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
8395 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
8396 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
8397 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
8398 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
8399 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
8400 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
8401 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
8402 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
8403 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8404 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
8405 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
8406 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
8407 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
8408 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
8409 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8410 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8411 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8412 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
8413 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
8414 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
8415 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
8416 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
8417 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
8418 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
8419 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
8420 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
8421 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
8422 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
8423 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
8424 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
8425 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
8426 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
8427 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
8428 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
8429 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
8430 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
8431 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
8432 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
8433 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
8434 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
8435 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
8436 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
8437 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
8438 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
8440 rt2800_normal_mode_setup_5xxx(rt2x00dev);
8442 rt2800_led_open_drain_enable(rt2x00dev);
8445 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
8447 rt2800_rf_init_calibration(rt2x00dev, 30);
8449 rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
8450 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
8451 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
8452 rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
8453 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8454 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
8455 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
8456 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
8457 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
8458 rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
8459 rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
8460 rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
8461 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
8462 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8463 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
8464 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
8465 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
8466 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
8467 rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
8468 rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
8469 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
8471 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
8474 rt2800_freq_cal_mode1(rt2x00dev);
8477 if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
8478 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
8480 rt2800_normal_mode_setup_5xxx(rt2x00dev);
8482 if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
8483 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
8485 rt2800_led_open_drain_enable(rt2x00dev);
8488 static void rt2800_rf_self_txdc_cal(struct rt2x00_dev *rt2x00dev)
8494 mac0518 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
8495 mac051c = rt2800_register_read(rt2x00dev, RF_BYPASS0);
8496 mac0528 = rt2800_register_read(rt2x00dev, RF_CONTROL2);
8497 mac052c = rt2800_register_read(rt2x00dev, RF_BYPASS2);
8499 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x0);
8500 rt2800_register_write(rt2x00dev, RF_BYPASS2, 0x0);
8502 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0xC);
8503 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x3306);
8504 rt2800_register_write(rt2x00dev, RF_CONTROL2, 0x3330);
8505 rt2800_register_write(rt2x00dev, RF_BYPASS2, 0xfffff);
8506 rfb5r1_org = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
8507 rfb7r1_org = rt2800_rfcsr_read_bank(rt2x00dev, 7, 1);
8509 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, 0x4);
8512 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
8516 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rfb5r1_org);
8518 rt2800_rfcsr_write_bank(rt2x00dev, 7, 1, 0x4);
8521 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 1);
8525 rt2800_rfcsr_write_bank(rt2x00dev, 7, 1, rfb7r1_org);
8527 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x0);
8528 rt2800_register_write(rt2x00dev, RF_BYPASS2, 0x0);
8529 rt2800_register_write(rt2x00dev, RF_CONTROL0, mac0518);
8530 rt2800_register_write(rt2x00dev, RF_BYPASS0, mac051c);
8531 rt2800_register_write(rt2x00dev, RF_CONTROL2, mac0528);
8532 rt2800_register_write(rt2x00dev, RF_BYPASS2, mac052c);
8535 static int rt2800_calcrcalibrationcode(struct rt2x00_dev *rt2x00dev, int d1, int d2)
8546 static void rt2800_r_calibration(struct rt2x00_dev *rt2x00dev)
8561 saverfb0r1 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
8562 saverfb0r34 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 34);
8563 saverfb0r35 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);
8564 saverfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
8565 saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
8566 saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
8567 saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
8568 saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
8570 savebbpr22 = rt2800_bbp_read(rt2x00dev, 22);
8571 savebbpr47 = rt2800_bbp_read(rt2x00dev, 47);
8572 savebbpr49 = rt2800_bbp_read(rt2x00dev, 49);
8574 savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
8575 MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
8576 MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
8577 MAC_PWR_PIN_CFG = rt2800_register_read(rt2x00dev, PWR_PIN_CFG);
8579 maccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
8581 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg);
8583 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))
8584 rt2x00_warn(rt2x00dev, "Wait MAC Tx Status to MAX !!!\n");
8586 maccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
8588 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg);
8590 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX)))
8591 rt2x00_warn(rt2x00dev, "Wait MAC Rx Status to MAX !!!\n");
8594 rt2800_register_write(rt2x00dev, RF_BYPASS0, rfvalue);
8596 rt2800_register_write(rt2x00dev, RF_CONTROL0, rfvalue);
8598 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, 0x27);
8599 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, 0x80);
8600 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0x83);
8601 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x00);
8602 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x20);
8604 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x00);
8605 rt2800_rfcsr_write_bank(rt2x00dev, 0, 34, 0x13);
8606 rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);
8608 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x1);
8610 rt2800_bbp_write(rt2x00dev, 47, 0x04);
8611 rt2800_bbp_write(rt2x00dev, 22, 0x80);
8613 bytevalue = rt2800_bbp_read(rt2x00dev, 49);
8618 rt2800_bbp_write(rt2x00dev, 22, 0x0);
8619 rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x01);
8621 rt2800_bbp_write(rt2x00dev, 22, 0x80);
8623 bytevalue = rt2800_bbp_read(rt2x00dev, 49);
8628 rt2800_bbp_write(rt2x00dev, 22, 0x0);
8630 rcalcode = rt2800_calcrcalibrationcode(rt2x00dev, d1, d2);
8636 rt2800_rfcsr_write_bank(rt2x00dev, 0, 7, r_cal_code);
8638 rt2800_bbp_write(rt2x00dev, 22, 0x0);
8640 bytevalue = rt2800_bbp_read(rt2x00dev, 21);
8642 rt2800_bbp_write(rt2x00dev, 21, bytevalue);
8643 bytevalue = rt2800_bbp_read(rt2x00dev, 21);
8645 rt2800_bbp_write(rt2x00dev, 21, bytevalue);
8647 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, saverfb0r1);
8648 rt2800_rfcsr_write_bank(rt2x00dev, 0, 34, saverfb0r34);
8649 rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, saverfb0r35);
8650 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r4);
8651 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17);
8652 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18);
8653 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19);
8654 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20);
8656 rt2800_bbp_write(rt2x00dev, 22, savebbpr22);
8657 rt2800_bbp_write(rt2x00dev, 47, savebbpr47);
8658 rt2800_bbp_write(rt2x00dev, 49, savebbpr49);
8660 rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0);
8661 rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0);
8663 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
8664 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, MAC_PWR_PIN_CFG);
8667 static void rt2800_rxdcoc_calibration(struct rt2x00_dev *rt2x00dev)
8674 saverfb0r2 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
8677 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfvalue);
8679 rt2800_bbp_write(rt2x00dev, 158, 141);
8680 bbpreg = rt2800_bbp_read(rt2x00dev, 159);
8682 rt2800_bbp_write(rt2x00dev, 159, bbpreg);
8684 macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
8685 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x8);
8687 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))
8688 rt2x00_warn(rt2x00dev, "RF TX busy in RX RXDCOC calibration\n");
8690 saverfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
8691 saverfb7r4 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4);
8694 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x64);
8695 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r4);
8696 rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, saverfb7r4);
8698 rt2800_bbp_write(rt2x00dev, 158, 140);
8699 bbpreg = rt2800_bbp_read(rt2x00dev, 159);
8701 rt2800_bbp_write(rt2x00dev, 159, bbpreg);
8703 rt2800_bbp_write(rt2x00dev, 159, bbpreg);
8706 bbpreg = rt2800_bbp_read(rt2x00dev, 159);
8712 bbpreg = rt2800_bbp_read(rt2x00dev, 159);
8714 rt2800_bbp_write(rt2x00dev, 159, bbpreg);
8716 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
8718 rt2800_bbp_write(rt2x00dev, 158, 141);
8719 bbpreg = rt2800_bbp_read(rt2x00dev, 159);
8721 rt2800_bbp_write(rt2x00dev, 159, bbpreg);
8723 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, saverfb0r2);
8743 static void rt2800_rxiq_calibration(struct rt2x00_dev *rt2x00dev)
8771 savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
8772 orig_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
8773 orig_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
8774 orig_RF_CONTROL1 = rt2800_register_read(rt2x00dev, RF_CONTROL1);
8775 orig_RF_BYPASS1 = rt2800_register_read(rt2x00dev, RF_BYPASS1);
8776 orig_RF_CONTROL3 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
8777 orig_RF_BYPASS3 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
8779 bbp1 = rt2800_bbp_read(rt2x00dev, 1);
8780 bbp4 = rt2800_bbp_read(rt2x00dev, 4);
8782 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x0);
8784 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY)))
8785 rt2x00_warn(rt2x00dev, "Timeout waiting for MAC status in RXIQ calibration\n");
8789 rt2800_bbp_write(rt2x00dev, 4, bbpval);
8791 bbpval = rt2800_bbp_read(rt2x00dev, 21);
8793 rt2800_bbp_write(rt2x00dev, 21, bbpval);
8795 rt2800_bbp_write(rt2x00dev, 21, bbpval);
8797 rt2800_register_write(rt2x00dev, RF_CONTROL1, 0x00000202);
8798 rt2800_register_write(rt2x00dev, RF_BYPASS1, 0x00000303);
8799 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))
8800 rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0101);
8802 rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x0000);
8804 rt2800_register_write(rt2x00dev, RF_BYPASS3, 0xf1f1);
8806 rfb0r1 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
8807 rfb0r2 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
8808 rfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
8809 rfb4r0 = rt2800_rfcsr_read_bank(rt2x00dev, 4, 0);
8810 rfb4r19 = rt2800_rfcsr_read_bank(rt2x00dev, 4, 19);
8811 rfb5r3 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
8812 rfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
8813 rfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
8814 rfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
8815 rfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
8816 rfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
8818 rfb6r0 = rt2800_rfcsr_read_bank(rt2x00dev, 6, 0);
8819 rfb6r19 = rt2800_rfcsr_read_bank(rt2x00dev, 6, 19);
8820 rfb7r3 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 3);
8821 rfb7r4 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4);
8822 rfb7r17 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 17);
8823 rfb7r18 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 18);
8824 rfb7r19 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 19);
8825 rfb7r20 = rt2800_rfcsr_read_bank(rt2x00dev, 7, 20);
8827 rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x87);
8828 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0x27);
8829 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x38);
8830 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x38);
8831 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x80);
8832 rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0xC1);
8833 rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x60);
8834 rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
8836 rt2800_bbp_write(rt2x00dev, 23, 0x0);
8837 rt2800_bbp_write(rt2x00dev, 24, 0x0);
8839 rt2800_bbp_dcoc_write(rt2x00dev, 5, 0x0);
8841 bbpr241 = rt2800_bbp_read(rt2x00dev, 241);
8842 bbpr242 = rt2800_bbp_read(rt2x00dev, 242);
8844 rt2800_bbp_write(rt2x00dev, 241, 0x10);
8845 rt2800_bbp_write(rt2x00dev, 242, 0x84);
8846 rt2800_bbp_write(rt2x00dev, 244, 0x31);
8848 bbpval = rt2800_bbp_dcoc_read(rt2x00dev, 3);
8850 rt2800_bbp_dcoc_write(rt2x00dev, 3, bbpval);
8852 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
8854 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000006);
8856 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003376);
8857 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001006);
8859 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
8860 rt2800_bbp_write(rt2x00dev, 23, 0x06);
8861 rt2800_bbp_write(rt2x00dev, 24, 0x06);
8863 rt2800_bbp_write(rt2x00dev, 23, 0x02);
8864 rt2800_bbp_write(rt2x00dev, 24, 0x02);
8871 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfval);
8874 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfval);
8877 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfval);
8879 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001006);
8884 rt2800_bbp_write(rt2x00dev, 1, bbpval);
8886 rt2800_bbp_dcoc_write(rt2x00dev, 1, 0x00);
8890 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfval);
8893 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfval);
8896 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfval);
8898 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002006);
8903 rt2800_bbp_write(rt2x00dev, 1, bbpval);
8905 rt2800_bbp_dcoc_write(rt2x00dev, 1, 0x01);
8911 rt2800_rfcsr_write_dccal(rt2x00dev, 3, rf_vga_table[vga_idx]);
8912 rt2800_rfcsr_write_dccal(rt2x00dev, 4, rf_vga_table[vga_idx]);
8914 rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x93);
8917 bbpval = rt2800_bbp_read(rt2x00dev, 159);
8925 rt2x00_warn(rt2x00dev, "Fatal Error: Calibration doesn't finish");
8933 rt2800_bbp_write(rt2x00dev, 158, 0x1e);
8934 rt2800_bbp_write(rt2x00dev, 159, i);
8935 rt2800_bbp_write(rt2x00dev, 158, 0x22);
8936 value = rt2800_bbp_read(rt2x00dev, 159);
8938 rt2800_bbp_write(rt2x00dev, 158, 0x21);
8939 value = rt2800_bbp_read(rt2x00dev, 159);
8941 rt2800_bbp_write(rt2x00dev, 158, 0x20);
8942 value = rt2800_bbp_read(rt2x00dev, 159);
8944 rt2800_bbp_write(rt2x00dev, 158, 0x1f);
8945 value = rt2800_bbp_read(rt2x00dev, 159);
8966 rt2x00_dbg(rt2x00dev,
8997 rt2x00_dbg(rt2x00dev, "Sigma_i=%d, Sigma_q=%d, R_iq=%d", sigma_i, sigma_q, r_iq);
9005 rt2x00_dbg(rt2x00dev, "RXIQ Sigma_i=%d, Sigma_q=%d, R_iq=%d\n",
9014 rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL");
9019 rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL");
9024 rt2x00_dbg(rt2x00dev, "RXIQ Sigma_i=%d, Sigma_q=%d, R_iq=%d\n",
9026 rt2x00_warn(rt2x00dev, "RXIQ calibration FAIL");
9030 rt2800_bbp_write(rt2x00dev, 158, 0x37);
9031 rt2800_bbp_write(rt2x00dev, 159, g_imb & 0x3f);
9032 rt2800_bbp_write(rt2x00dev, 158, 0x35);
9033 rt2800_bbp_write(rt2x00dev, 159, ph_rx & 0x3f);
9035 rt2800_bbp_write(rt2x00dev, 158, 0x55);
9036 rt2800_bbp_write(rt2x00dev, 159, g_imb & 0x3f);
9037 rt2800_bbp_write(rt2x00dev, 158, 0x53);
9038 rt2800_bbp_write(rt2x00dev, 159, ph_rx & 0x3f);
9043 rt2800_bbp_write(rt2x00dev, 158, 0x3);
9044 bbpval = rt2800_bbp_read(rt2x00dev, 159);
9045 rt2800_bbp_write(rt2x00dev, 159, (bbpval | 0x07));
9047 rt2800_bbp_write(rt2x00dev, 158, 0x00);
9048 rt2800_bbp_write(rt2x00dev, 159, 0x00);
9049 rt2800_bbp_write(rt2x00dev, 1, bbp1);
9050 rt2800_bbp_write(rt2x00dev, 4, bbp4);
9051 rt2800_bbp_write(rt2x00dev, 241, bbpr241);
9052 rt2800_bbp_write(rt2x00dev, 242, bbpr242);
9054 rt2800_bbp_write(rt2x00dev, 244, 0x00);
9055 bbpval = rt2800_bbp_read(rt2x00dev, 21);
9057 rt2800_bbp_write(rt2x00dev, 21, bbpval);
9060 rt2800_bbp_write(rt2x00dev, 21, bbpval);
9062 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, rfb0r1);
9063 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, rfb0r2);
9064 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42);
9066 rt2800_rfcsr_write_bank(rt2x00dev, 4, 0, rfb4r0);
9067 rt2800_rfcsr_write_bank(rt2x00dev, 4, 19, rfb4r19);
9068 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rfb5r3);
9069 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rfb5r4);
9070 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rfb5r17);
9071 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, rfb5r18);
9072 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, rfb5r19);
9073 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, rfb5r20);
9075 rt2800_rfcsr_write_bank(rt2x00dev, 6, 0, rfb6r0);
9076 rt2800_rfcsr_write_bank(rt2x00dev, 6, 19, rfb6r19);
9077 rt2800_rfcsr_write_bank(rt2x00dev, 7, 3, rfb7r3);
9078 rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, rfb7r4);
9079 rt2800_rfcsr_write_bank(rt2x00dev, 7, 17, rfb7r17);
9080 rt2800_rfcsr_write_bank(rt2x00dev, 7, 18, rfb7r18);
9081 rt2800_rfcsr_write_bank(rt2x00dev, 7, 19, rfb7r19);
9082 rt2800_rfcsr_write_bank(rt2x00dev, 7, 20, rfb7r20);
9084 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000006);
9086 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
9088 rt2800_register_write(rt2x00dev, RF_CONTROL0, orig_RF_CONTROL0);
9090 rt2800_register_write(rt2x00dev, RF_BYPASS0, orig_RF_BYPASS0);
9091 rt2800_register_write(rt2x00dev, RF_CONTROL1, orig_RF_CONTROL1);
9092 rt2800_register_write(rt2x00dev, RF_BYPASS1, orig_RF_BYPASS1);
9093 rt2800_register_write(rt2x00dev, RF_CONTROL3, orig_RF_CONTROL3);
9094 rt2800_register_write(rt2x00dev, RF_BYPASS3, orig_RF_BYPASS3);
9095 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
9098 static void rt2800_rf_configstore(struct rt2x00_dev *rt2x00dev,
9104 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
9108 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
9112 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);
9116 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
9120 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 0);
9124 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 2);
9128 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 34);
9132 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
9136 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
9140 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
9144 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
9148 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
9152 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
9157 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
9161 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
9165 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);
9169 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
9173 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 0);
9177 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 2);
9181 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 34);
9185 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 3);
9189 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4);
9193 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 17);
9197 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 18);
9201 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 19);
9205 rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 20);
9210 rt2x00_warn(rt2x00dev, "Unknown chain = %u\n", chain);
9214 static void rt2800_rf_configrecover(struct rt2x00_dev *rt2x00dev,
9225 rt2800_rfcsr_write_bank(rt2x00dev, bank, rf_register, value);
9226 rt2x00_dbg(rt2x00dev, "bank: %d, rf_register: %d, value: %x\n",
9232 static void rt2800_setbbptonegenerator(struct rt2x00_dev *rt2x00dev)
9234 rt2800_bbp_write(rt2x00dev, 158, 0xAA);
9235 rt2800_bbp_write(rt2x00dev, 159, 0x00);
9237 rt2800_bbp_write(rt2x00dev, 158, 0xAB);
9238 rt2800_bbp_write(rt2x00dev, 159, 0x0A);
9240 rt2800_bbp_write(rt2x00dev, 158, 0xAC);
9241 rt2800_bbp_write(rt2x00dev, 159, 0x3F);
9243 rt2800_bbp_write(rt2x00dev, 158, 0xAD);
9244 rt2800_bbp_write(rt2x00dev, 159, 0x3F);
9246 rt2800_bbp_write(rt2x00dev, 244, 0x40);
9249 static u32 rt2800_do_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx, u8 read_neg)
9257 rt2800_bbp_write(rt2x00dev, 158, 0x00);
9258 rt2800_bbp_write(rt2x00dev, 159, 0x9b);
9264 bbp = rt2800_bbp_read(rt2x00dev, 159);
9268 rt2800_bbp_write(rt2x00dev, 158, 0xba);
9269 rt2800_bbp_write(rt2x00dev, 159, tidx);
9270 rt2800_bbp_write(rt2x00dev, 159, tidx);
9271 rt2800_bbp_write(rt2x00dev, 159, tidx);
9273 macvalue = rt2800_register_read(rt2x00dev, 0x057C);
9282 rt2x00_dbg(rt2x00dev, "I = %d, Q = %d, power = %x\n", fftout_i, fftout_q, pint);
9288 rt2800_bbp_write(rt2x00dev, 158, 0xba);
9289 rt2800_bbp_write(rt2x00dev, 159, tidxi);
9290 rt2800_bbp_write(rt2x00dev, 159, tidxi);
9291 rt2800_bbp_write(rt2x00dev, 159, tidxi);
9293 macvalue = rt2800_register_read(rt2x00dev, 0x057C);
9308 static u32 rt2800_read_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx)
9314 rt2800_bbp_write(rt2x00dev, 158, 0xBA);
9315 rt2800_bbp_write(rt2x00dev, 159, tidx);
9316 rt2800_bbp_write(rt2x00dev, 159, tidx);
9317 rt2800_bbp_write(rt2x00dev, 159, tidx);
9319 macvalue = rt2800_register_read(rt2x00dev, 0x057C);
9332 static void rt2800_write_dc(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 alc, u8 iorq, u8 dc)
9336 rt2800_bbp_write(rt2x00dev, 158, 0xb0);
9338 rt2800_bbp_write(rt2x00dev, 159, bbp);
9345 rt2800_bbp_write(rt2x00dev, 158, bbp);
9347 rt2800_bbp_write(rt2x00dev, 159, bbp);
9350 static void rt2800_loft_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx,
9360 rt2800_bbp_write(rt2x00dev, 158, 0xb0);
9361 rt2800_bbp_write(rt2x00dev, 159, 0x80);
9371 rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx0);
9372 p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
9377 rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx1);
9378 p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
9380 rt2x00_dbg(rt2x00dev, "alc=%u, IorQ=%u, idx_final=%2x\n",
9382 rt2x00_dbg(rt2x00dev, "p0=%x, p1=%x, pf=%x, idx_0=%x, idx_1=%x, ibit=%x\n",
9394 rt2x00_dbg(rt2x00dev, "IorQ=%u, idx_final[%u]:%x, pf:%8x\n",
9397 rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idxf[iorq]);
9405 static void rt2800_iq_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 *ges, u8 *pes)
9440 rt2800_bbp_write(rt2x00dev, 158, bbp);
9441 rt2800_bbp_write(rt2x00dev, 159, idx0);
9443 p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
9452 rt2800_bbp_write(rt2x00dev, 158, bbp);
9453 rt2800_bbp_write(rt2x00dev, 159, idx1);
9455 p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
9457 rt2x00_dbg(rt2x00dev,
9474 rt2800_bbp_write(rt2x00dev, 158, bbp);
9475 rt2800_bbp_write(rt2x00dev, 159, iq_err);
9482 rt2x00_dbg(rt2x00dev, "IQCalibration pf=%8x (%2x, %2x) !\n",
9504 rt2800_bbp_write(rt2x00dev, 158, bbp);
9505 rt2800_bbp_write(rt2x00dev, 159, gef & 0x0F);
9508 rt2800_bbp_write(rt2x00dev, 158, bbp);
9509 rt2800_bbp_write(rt2x00dev, 159, pef & 0x3F);
9511 p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
9521 rt2x00_dbg(rt2x00dev, "Fine IQCalibration p1=%8x pf=%8x (%2x, %2x) !\n",
9529 static void rt2800_rf_aux_tx0_loopback(struct rt2x00_dev *rt2x00dev)
9531 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x21);
9532 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, 0x10);
9533 rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);
9534 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x1b);
9535 rt2800_rfcsr_write_bank(rt2x00dev, 4, 0, 0x81);
9536 rt2800_rfcsr_write_bank(rt2x00dev, 4, 2, 0x81);
9537 rt2800_rfcsr_write_bank(rt2x00dev, 4, 34, 0xee);
9538 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, 0x2d);
9539 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, 0x2d);
9540 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, 0x80);
9541 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xd7);
9542 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0xa2);
9543 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x20);
9546 static void rt2800_rf_aux_tx1_loopback(struct rt2x00_dev *rt2x00dev)
9548 rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x22);
9549 rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, 0x20);
9550 rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);
9551 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x4b);
9552 rt2800_rfcsr_write_bank(rt2x00dev, 6, 0, 0x81);
9553 rt2800_rfcsr_write_bank(rt2x00dev, 6, 2, 0x81);
9554 rt2800_rfcsr_write_bank(rt2x00dev, 6, 34, 0xee);
9555 rt2800_rfcsr_write_bank(rt2x00dev, 7, 3, 0x2d);
9556 rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, 0x2d);
9557 rt2800_rfcsr_write_bank(rt2x00dev, 7, 17, 0x80);
9558 rt2800_rfcsr_write_bank(rt2x00dev, 7, 18, 0xd7);
9559 rt2800_rfcsr_write_bank(rt2x00dev, 7, 19, 0xa2);
9560 rt2800_rfcsr_write_bank(rt2x00dev, 7, 20, 0x20);
9563 static void rt2800_loft_iq_calibration(struct rt2x00_dev *rt2x00dev)
9597 savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9598 macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
9599 macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
9600 macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
9601 macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
9602 macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
9603 mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8);
9604 orig528 = rt2800_register_read(rt2x00dev, RF_CONTROL2);
9605 orig52c = rt2800_register_read(rt2x00dev, RF_BYPASS2);
9607 macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9609 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
9611 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))
9612 rt2x00_warn(rt2x00dev, "RF TX busy in LOFT IQ calibration\n");
9614 macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9616 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
9618 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX)))
9619 rt2x00_warn(rt2x00dev, "RF RX busy in LOFT IQ calibration\n");
9622 rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx);
9624 bbpr30 = rt2800_bbp_read(rt2x00dev, 30);
9625 rfb0r39 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 39);
9626 rfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
9628 rt2800_bbp_write(rt2x00dev, 30, 0x1F);
9629 rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, 0x80);
9630 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x5B);
9632 rt2800_bbp_write(rt2x00dev, 23, 0x00);
9633 rt2800_bbp_write(rt2x00dev, 24, 0x00);
9635 rt2800_setbbptonegenerator(rt2x00dev);
9638 rt2800_bbp_write(rt2x00dev, 23, 0x00);
9639 rt2800_bbp_write(rt2x00dev, 24, 0x00);
9640 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00);
9641 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F);
9642 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
9643 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306);
9644 rt2800_register_write(rt2x00dev, 0x13b8, 0x10);
9648 rt2800_rf_aux_tx0_loopback(rt2x00dev);
9650 rt2800_rf_aux_tx1_loopback(rt2x00dev);
9655 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004);
9657 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004);
9659 rt2800_bbp_write(rt2x00dev, 158, 0x05);
9660 rt2800_bbp_write(rt2x00dev, 159, 0x00);
9662 rt2800_bbp_write(rt2x00dev, 158, 0x01);
9664 rt2800_bbp_write(rt2x00dev, 159, 0x00);
9666 rt2800_bbp_write(rt2x00dev, 159, 0x01);
9670 rt2800_bbp_write(rt2x00dev, 23, bbp_2324gain[rf_alc_idx]);
9671 rt2800_bbp_write(rt2x00dev, 24, bbp_2324gain[rf_alc_idx]);
9673 macvalue = rt2800_register_read(rt2x00dev, RF_CONTROL3);
9677 rt2800_register_write(rt2x00dev, RF_CONTROL3, macvalue);
9679 rt2800_register_write(rt2x00dev, RF_BYPASS3, macvalue);
9682 rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x21);
9686 rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
9687 rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
9688 rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00);
9689 rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00);
9690 p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
9691 rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x21);
9692 p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
9693 rt2x00_dbg(rt2x00dev, "LOFT AGC %d %d\n", p0, p1);
9698 rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00);
9699 rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00);
9701 rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n", vga_gain[ch_idx],
9710 rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
9711 rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
9713 rt2800_loft_search(rt2x00dev, ch_idx, rf_alc_idx, loft_dc_search_result);
9719 rt2800_bbp_write(rt2x00dev, 158, 0xB0);
9721 rt2800_bbp_write(rt2x00dev, 159, bbp);
9722 rt2x00_dbg(rt2x00dev, " ALC %2x,", bbp);
9724 rt2800_bbp_write(rt2x00dev, 158, 0xb1);
9727 rt2800_bbp_write(rt2x00dev, 159, bbp);
9728 rt2x00_dbg(rt2x00dev, " I0 %2x,", bbp);
9730 rt2800_bbp_write(rt2x00dev, 158, 0xb2);
9733 rt2800_bbp_write(rt2x00dev, 159, bbp);
9734 rt2x00_dbg(rt2x00dev, " Q0 %2x,", bbp);
9736 rt2800_bbp_write(rt2x00dev, 158, 0xb8);
9739 rt2800_bbp_write(rt2x00dev, 159, bbp);
9740 rt2x00_dbg(rt2x00dev, " I1 %2x,", bbp);
9742 rt2800_bbp_write(rt2x00dev, 158, 0xb9);
9745 rt2800_bbp_write(rt2x00dev, 159, bbp);
9746 rt2x00_dbg(rt2x00dev, " Q1 %2x\n", bbp);
9750 rt2800_bbp_write(rt2x00dev, 23, 0x00);
9751 rt2800_bbp_write(rt2x00dev, 24, 0x00);
9753 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
9755 rt2800_bbp_write(rt2x00dev, 158, 0x00);
9756 rt2800_bbp_write(rt2x00dev, 159, 0x00);
9759 rt2800_bbp_write(rt2x00dev, 244, 0x00);
9761 rt2800_bbp_write(rt2x00dev, 21, 0x01);
9763 rt2800_bbp_write(rt2x00dev, 21, 0x00);
9765 rt2800_rf_configrecover(rt2x00dev, rf_store);
9767 rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1);
9768 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
9769 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00);
9770 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00);
9771 rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2);
9773 rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3);
9774 rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4);
9775 rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5);
9776 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
9777 rt2800_register_write(rt2x00dev, RF_CONTROL2, orig528);
9778 rt2800_register_write(rt2x00dev, RF_BYPASS2, orig52c);
9779 rt2800_register_write(rt2x00dev, 0x13b8, mac13b8);
9781 savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9782 macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
9783 macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
9784 macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
9785 macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
9786 macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
9788 bbpr1 = rt2800_bbp_read(rt2x00dev, 1);
9789 bbpr4 = rt2800_bbp_read(rt2x00dev, 4);
9790 bbpr241 = rt2800_bbp_read(rt2x00dev, 241);
9791 bbpr242 = rt2800_bbp_read(rt2x00dev, 242);
9792 mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8);
9794 macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9796 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
9798 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))
9799 rt2x00_warn(rt2x00dev, "RF TX busy in LOFT IQ calibration\n");
9801 macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
9803 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
9805 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX)))
9806 rt2x00_warn(rt2x00dev, "RF RX busy in LOFT IQ calibration\n");
9808 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9809 rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000101);
9810 rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1);
9813 rt2800_bbp_write(rt2x00dev, 23, 0x00);
9814 rt2800_bbp_write(rt2x00dev, 24, 0x00);
9816 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9817 rt2800_bbp_write(rt2x00dev, 4, bbpr4 & (~0x18));
9818 rt2800_bbp_write(rt2x00dev, 21, 0x01);
9820 rt2800_bbp_write(rt2x00dev, 21, 0x00);
9822 rt2800_bbp_write(rt2x00dev, 241, 0x14);
9823 rt2800_bbp_write(rt2x00dev, 242, 0x80);
9824 rt2800_bbp_write(rt2x00dev, 244, 0x31);
9826 rt2800_setbbptonegenerator(rt2x00dev);
9829 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
9830 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306);
9833 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F);
9835 if (!test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9836 rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000000);
9837 rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1);
9840 rt2800_register_write(rt2x00dev, 0x13b8, 0x00000010);
9843 rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx);
9845 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x3B);
9846 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x3B);
9848 rt2800_bbp_write(rt2x00dev, 158, 0x03);
9849 rt2800_bbp_write(rt2x00dev, 159, 0x60);
9850 rt2800_bbp_write(rt2x00dev, 158, 0xB0);
9851 rt2800_bbp_write(rt2x00dev, 159, 0x80);
9854 rt2800_bbp_write(rt2x00dev, 23, 0x00);
9855 rt2800_bbp_write(rt2x00dev, 24, 0x00);
9858 rt2800_bbp_write(rt2x00dev, 158, 0x01);
9859 rt2800_bbp_write(rt2x00dev, 159, 0x00);
9860 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9863 rt2800_bbp_write(rt2x00dev, 1, bbp);
9865 rt2800_rf_aux_tx0_loopback(rt2x00dev);
9866 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004);
9868 rt2800_bbp_write(rt2x00dev, 158, 0x01);
9869 rt2800_bbp_write(rt2x00dev, 159, 0x01);
9870 if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags)) {
9873 rt2800_bbp_write(rt2x00dev, 1, bbp);
9875 rt2800_rf_aux_tx1_loopback(rt2x00dev);
9876 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004);
9879 rt2800_bbp_write(rt2x00dev, 158, 0x05);
9880 rt2800_bbp_write(rt2x00dev, 159, 0x04);
9883 rt2800_bbp_write(rt2x00dev, 158, bbp);
9884 rt2800_bbp_write(rt2x00dev, 159, 0x00);
9886 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9887 rt2800_bbp_write(rt2x00dev, 23, 0x06);
9888 rt2800_bbp_write(rt2x00dev, 24, 0x06);
9891 rt2800_bbp_write(rt2x00dev, 23, 0x1F);
9892 rt2800_bbp_write(rt2x00dev, 24, 0x1F);
9898 rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
9899 rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
9902 rt2800_bbp_write(rt2x00dev, 158, bbp);
9903 rt2800_bbp_write(rt2x00dev, 159, 0x00);
9904 p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0);
9905 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))
9906 p0_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A);
9909 rt2800_bbp_write(rt2x00dev, 158, bbp);
9910 rt2800_bbp_write(rt2x00dev, 159, 0x21);
9911 p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0);
9912 if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags))
9913 p1_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A);
9915 rt2x00_dbg(rt2x00dev, "IQ AGC %d %d\n", p0, p1);
9917 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9918 rt2x00_dbg(rt2x00dev, "IQ AGC IDX 10 %d %d\n", p0_idx10, p1_idx10);
9932 rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n", vga_gain[ch_idx],
9936 rt2800_bbp_write(rt2x00dev, 158, bbp);
9937 rt2800_bbp_write(rt2x00dev, 159, 0x00);
9939 rt2800_iq_search(rt2x00dev, ch_idx, ger, per);
9942 rt2800_bbp_write(rt2x00dev, 23, 0x00);
9943 rt2800_bbp_write(rt2x00dev, 24, 0x00);
9944 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
9946 rt2800_bbp_write(rt2x00dev, 158, 0x28);
9948 rt2800_bbp_write(rt2x00dev, 159, bbp);
9950 rt2800_bbp_write(rt2x00dev, 158, 0x29);
9952 rt2800_bbp_write(rt2x00dev, 159, bbp);
9954 rt2800_bbp_write(rt2x00dev, 158, 0x46);
9956 rt2800_bbp_write(rt2x00dev, 159, bbp);
9958 rt2800_bbp_write(rt2x00dev, 158, 0x47);
9960 rt2800_bbp_write(rt2x00dev, 159, bbp);
9962 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
9963 rt2800_bbp_write(rt2x00dev, 1, bbpr1);
9964 rt2800_bbp_write(rt2x00dev, 241, bbpr241);
9965 rt2800_bbp_write(rt2x00dev, 242, bbpr242);
9967 rt2800_bbp_write(rt2x00dev, 244, 0x00);
9969 rt2800_bbp_write(rt2x00dev, 158, 0x00);
9970 rt2800_bbp_write(rt2x00dev, 159, 0x00);
9971 rt2800_bbp_write(rt2x00dev, 158, 0xB0);
9972 rt2800_bbp_write(rt2x00dev, 159, 0x00);
9974 rt2800_bbp_write(rt2x00dev, 30, bbpr30);
9975 rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, rfb0r39);
9976 rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42);
9978 if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))
9979 rt2800_bbp_write(rt2x00dev, 4, bbpr4);
9981 rt2800_bbp_write(rt2x00dev, 21, 0x01);
9983 rt2800_bbp_write(rt2x00dev, 21, 0x00);
9985 rt2800_rf_configrecover(rt2x00dev, rf_store);
9987 rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1);
9988 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00);
9989 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00);
9990 rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2);
9992 rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3);
9993 rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4);
9994 rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5);
9995 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
9996 rt2800_register_write(rt2x00dev, 0x13b8, mac13b8);
9999 static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
10004 bbp_val = rt2800_bbp_read(rt2x00dev, 21);
10006 rt2800_bbp_write(rt2x00dev, 21, bbp_val);
10010 bbp_val = rt2800_bbp_read(rt2x00dev, 4);
10012 rt2800_bbp_write(rt2x00dev, 4, bbp_val);
10016 bbp_val = rt2800_bbp_read(rt2x00dev, 21);
10018 rt2800_bbp_write(rt2x00dev, 21, bbp_val);
10022 static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal)
10027 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
10029 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02);
10031 rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06);
10033 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
10035 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val);
10038 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1);
10039 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20);
10040 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
10041 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
10044 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
10045 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
10048 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
10049 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31);
10051 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1);
10052 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18);
10053 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
10054 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
10057 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
10058 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
10061 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
10067 static s8 rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev)
10073 rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82);
10078 bbp_val = rt2800_bbp_read(rt2x00dev, 159);
10085 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 0x39);
10093 static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev,
10096 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
10114 MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
10115 MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
10118 savebbpr23 = rt2800_bbp_read(rt2x00dev, 23);
10120 savebbp159r0 = rt2800_bbp_dcoc_read(rt2x00dev, 0);
10121 savebbp159r2 = rt2800_bbp_dcoc_read(rt2x00dev, 2);
10124 saverfb5r00 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
10125 saverfb5r01 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
10126 saverfb5r03 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
10127 saverfb5r04 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
10128 saverfb5r05 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 5);
10129 saverfb5r06 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
10130 saverfb5r07 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
10131 saverfb5r08 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8);
10132 saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
10133 saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
10134 saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
10135 saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
10137 saverfb5r37 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 37);
10138 saverfb5r38 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 38);
10139 saverfb5r39 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 39);
10140 saverfb5r40 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 40);
10141 saverfb5r41 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 41);
10142 saverfb5r42 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 42);
10143 saverfb5r43 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 43);
10144 saverfb5r44 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 44);
10145 saverfb5r45 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 45);
10146 saverfb5r46 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 46);
10148 saverfb5r58 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
10149 saverfb5r59 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
10151 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
10153 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
10155 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
10157 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val);
10162 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
10168 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
10171 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
10174 bbp_val = rt2800_bbp_read(rt2x00dev, 23);
10177 rt2800_bbp_write(rt2x00dev, 23, bbp_val);
10197 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8);
10202 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val);
10204 rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40);
10206 rt2800_rf_lp_config(rt2x00dev, btxcal);
10209 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
10211 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
10212 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
10214 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
10217 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
10219 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
10220 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
10222 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
10227 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2);
10229 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
10231 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
10233 cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
10235 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2);
10237 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
10240 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
10243 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
10244 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
10247 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
10249 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
10252 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
10253 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
10256 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
10261 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
10263 cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
10301 rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00);
10302 rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01);
10303 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03);
10304 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04);
10305 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05);
10306 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06);
10307 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07);
10308 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08);
10309 rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17);
10310 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18);
10311 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19);
10312 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20);
10314 rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37);
10315 rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38);
10316 rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39);
10317 rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40);
10318 rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41);
10319 rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42);
10320 rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43);
10321 rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44);
10322 rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45);
10323 rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46);
10325 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58);
10326 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59);
10328 rt2800_bbp_write(rt2x00dev, 23, savebbpr23);
10330 rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0);
10331 rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2);
10333 bbp_val = rt2800_bbp_read(rt2x00dev, 4);
10335 2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));
10336 rt2800_bbp_write(rt2x00dev, 4, bbp_val);
10338 rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0);
10339 rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0);
10342 static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev)
10345 rt2800_rfcsr_write(rt2x00dev, 0, 0x02);
10346 rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
10347 rt2800_rfcsr_write(rt2x00dev, 2, 0x33);
10348 rt2800_rfcsr_write(rt2x00dev, 3, 0xFF);
10349 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
10350 rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
10351 rt2800_rfcsr_write(rt2x00dev, 6, 0x00);
10352 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
10353 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
10354 rt2800_rfcsr_write(rt2x00dev, 9, 0x00);
10355 rt2800_rfcsr_write(rt2x00dev, 10, 0x00);
10356 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
10357 rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset);
10358 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
10359 rt2800_rfcsr_write(rt2x00dev, 14, 0x40);
10360 rt2800_rfcsr_write(rt2x00dev, 15, 0x22);
10361 rt2800_rfcsr_write(rt2x00dev, 16, 0x4C);
10362 rt2800_rfcsr_write(rt2x00dev, 17, 0x00);
10363 rt2800_rfcsr_write(rt2x00dev, 18, 0x00);
10364 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
10365 rt2800_rfcsr_write(rt2x00dev, 20, 0xA0);
10366 rt2800_rfcsr_write(rt2x00dev, 21, 0x12);
10367 rt2800_rfcsr_write(rt2x00dev, 22, 0x07);
10368 rt2800_rfcsr_write(rt2x00dev, 23, 0x13);
10369 rt2800_rfcsr_write(rt2x00dev, 24, 0xFE);
10370 rt2800_rfcsr_write(rt2x00dev, 25, 0x24);
10371 rt2800_rfcsr_write(rt2x00dev, 26, 0x7A);
10372 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
10373 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
10374 rt2800_rfcsr_write(rt2x00dev, 29, 0x05);
10375 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
10376 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
10377 rt2800_rfcsr_write(rt2x00dev, 32, 0x00);
10378 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
10379 rt2800_rfcsr_write(rt2x00dev, 34, 0x00);
10380 rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
10381 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
10382 rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
10383 rt2800_rfcsr_write(rt2x00dev, 38, 0x00);
10384 rt2800_rfcsr_write(rt2x00dev, 39, 0x00);
10385 rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
10386 rt2800_rfcsr_write(rt2x00dev, 41, 0xD0);
10387 rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
10388 rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
10390 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
10391 if (rt2800_clk_is_20mhz(rt2x00dev))
10392 rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
10394 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
10395 rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
10396 rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
10397 rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
10398 rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
10399 rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
10400 rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
10401 rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
10402 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
10403 rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
10404 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
10405 rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
10406 rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
10407 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
10408 rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
10409 rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
10410 rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
10412 rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
10413 rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
10414 rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
10417 rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);
10418 rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00);
10419 rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00);
10420 rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00);
10421 rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00);
10422 rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08);
10423 rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00);
10424 rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51);
10425 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53);
10426 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16);
10427 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61);
10428 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
10429 rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22);
10430 rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D);
10431 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
10432 rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13);
10433 rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22);
10434 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27);
10435 rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02);
10436 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
10437 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01);
10438 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52);
10439 rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80);
10440 rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3);
10441 rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00);
10442 rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00);
10443 rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00);
10444 rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00);
10445 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C);
10446 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B);
10447 rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B);
10448 rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31);
10449 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D);
10450 rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00);
10451 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6);
10452 rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55);
10453 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00);
10454 rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB);
10455 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3);
10456 rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3);
10457 rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03);
10458 rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00);
10459 rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00);
10460 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3);
10461 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3);
10462 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
10463 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07);
10464 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68);
10465 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF);
10466 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C);
10467 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07);
10468 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8);
10469 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85);
10470 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10);
10471 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07);
10472 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A);
10473 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85);
10474 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10);
10475 rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C);
10476 rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00);
10478 rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);
10480 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
10481 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
10482 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
10483 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
10484 rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
10485 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
10486 rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
10487 rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
10488 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
10489 rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
10490 rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
10491 rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
10492 rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
10493 rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
10494 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
10495 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
10496 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
10497 rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
10498 rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);
10499 rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);
10500 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
10501 rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
10502 rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);
10503 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
10504 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
10505 rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
10506 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
10507 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
10508 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
10509 rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
10511 rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
10512 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
10513 rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
10514 rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
10515 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
10516 rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
10517 rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
10518 rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
10519 rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
10521 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
10522 rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
10523 rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
10524 rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
10525 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
10526 rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
10529 rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
10530 rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
10531 rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
10532 rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
10533 rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
10534 rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
10535 rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
10536 rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
10539 rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);
10540 rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00);
10541 rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00);
10542 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00);
10543 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00);
10544 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
10545 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
10546 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
10547 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
10548 rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00);
10549 rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07);
10550 rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01);
10551 rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07);
10552 rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07);
10553 rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07);
10554 rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20);
10555 rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22);
10556 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00);
10557 rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00);
10558 rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00);
10559 rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
10560 rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1);
10561 rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11);
10562 rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02);
10563 rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41);
10564 rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20);
10565 rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00);
10566 rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7);
10567 rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2);
10568 rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20);
10569 rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49);
10570 rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20);
10571 rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04);
10572 rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1);
10573 rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1);
10574 rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01);
10575 rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00);
10576 rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00);
10577 rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00);
10578 rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00);
10579 rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00);
10580 rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00);
10581 rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E);
10582 rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D);
10583 rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E);
10584 rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D);
10585 rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E);
10586 rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D);
10587 rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00);
10588 rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00);
10589 rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00);
10590 rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00);
10591 rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00);
10592 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
10593 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
10594 rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A);
10595 rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00);
10596 rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);
10597 rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);
10599 rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
10600 rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
10601 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
10603 rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
10604 rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
10606 rt2800_r_calibration(rt2x00dev);
10607 rt2800_rf_self_txdc_cal(rt2x00dev);
10608 rt2800_rxdcoc_calibration(rt2x00dev);
10609 rt2800_bw_filter_calibration(rt2x00dev, true);
10610 rt2800_bw_filter_calibration(rt2x00dev, false);
10611 rt2800_loft_iq_calibration(rt2x00dev);
10612 rt2800_rxiq_calibration(rt2x00dev);
10615 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
10617 if (rt2800_is_305x_soc(rt2x00dev)) {
10618 rt2800_init_rfcsr_305x_soc(rt2x00dev);
10622 switch (rt2x00dev->chip.rt) {
10626 rt2800_init_rfcsr_30xx(rt2x00dev);
10629 rt2800_init_rfcsr_3290(rt2x00dev);
10632 rt2800_init_rfcsr_3352(rt2x00dev);
10635 rt2800_init_rfcsr_3390(rt2x00dev);
10638 rt2800_init_rfcsr_3883(rt2x00dev);
10641 rt2800_init_rfcsr_3572(rt2x00dev);
10644 rt2800_init_rfcsr_3593(rt2x00dev);
10647 rt2800_init_rfcsr_5350(rt2x00dev);
10650 rt2800_init_rfcsr_5390(rt2x00dev);
10653 rt2800_init_rfcsr_5392(rt2x00dev);
10656 rt2800_init_rfcsr_5592(rt2x00dev);
10659 rt2800_init_rfcsr_6352(rt2x00dev);
10664 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
10672 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
10673 rt2800_init_registers(rt2x00dev)))
10679 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY)))
10685 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
10686 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
10687 if (rt2x00_is_usb(rt2x00dev))
10688 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
10689 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
10695 if (unlikely(rt2800_wait_bbp_ready(rt2x00dev)))
10701 rt2800_init_bbp(rt2x00dev);
10702 rt2800_init_rfcsr(rt2x00dev);
10704 if (rt2x00_is_usb(rt2x00dev) &&
10705 (rt2x00_rt(rt2x00dev, RT3070) ||
10706 rt2x00_rt(rt2x00dev, RT3071) ||
10707 rt2x00_rt(rt2x00dev, RT3572))) {
10709 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
10716 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
10719 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
10723 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
10727 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
10729 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
10732 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
10737 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF);
10738 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
10741 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF);
10742 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
10745 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY);
10746 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
10753 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
10757 rt2800_disable_wpdma(rt2x00dev);
10760 rt2800_wait_wpdma_ready(rt2x00dev);
10762 reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
10765 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
10769 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
10774 if (rt2x00_rt(rt2x00dev, RT3290))
10779 reg = rt2800_register_read(rt2x00dev, efuse_ctrl_reg);
10784 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
10793 if (rt2x00_rt(rt2x00dev, RT3290)) {
10806 mutex_lock(&rt2x00dev->csr_mutex);
10808 reg = rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg);
10812 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
10815 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, ®);
10817 reg = rt2800_register_read_lock(rt2x00dev, efuse_data3_reg);
10819 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
10820 reg = rt2800_register_read_lock(rt2x00dev, efuse_data2_reg);
10821 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
10822 reg = rt2800_register_read_lock(rt2x00dev, efuse_data1_reg);
10823 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
10824 reg = rt2800_register_read_lock(rt2x00dev, efuse_data0_reg);
10825 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
10827 mutex_unlock(&rt2x00dev->csr_mutex);
10830 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
10835 rt2800_efuse_read(rt2x00dev, i);
10841 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
10845 if (rt2x00_rt(rt2x00dev, RT3593) ||
10846 rt2x00_rt(rt2x00dev, RT3883))
10849 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG);
10856 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
10860 if (rt2x00_rt(rt2x00dev, RT3593) ||
10861 rt2x00_rt(rt2x00dev, RT3883))
10864 word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A);
10871 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
10873 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
10882 retval = rt2800_read_eeprom(rt2x00dev);
10889 mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
10890 rt2x00lib_set_mac_address(rt2x00dev, mac);
10892 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
10897 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
10898 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
10899 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
10900 rt2x00_rt(rt2x00dev, RT2872)) {
10906 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
10909 word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
10926 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
10927 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
10930 word = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
10933 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
10934 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
10940 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
10941 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
10942 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
10943 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
10944 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
10952 word = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
10955 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG);
10960 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
10962 drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
10964 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
10967 if (!rt2x00_rt(rt2x00dev, RT3593) &&
10968 !rt2x00_rt(rt2x00dev, RT3883)) {
10974 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
10976 drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
10978 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A);
10983 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
10985 word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
10988 if (!rt2x00_rt(rt2x00dev, RT3593) &&
10989 !rt2x00_rt(rt2x00dev, RT3883)) {
10995 rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
10997 if (rt2x00_rt(rt2x00dev, RT3593) ||
10998 rt2x00_rt(rt2x00dev, RT3883)) {
10999 word = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
11008 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
11014 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
11023 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
11030 if (rt2x00_rt(rt2x00dev, RT3290) ||
11031 rt2x00_rt(rt2x00dev, RT5390) ||
11032 rt2x00_rt(rt2x00dev, RT5392) ||
11033 rt2x00_rt(rt2x00dev, RT6352))
11034 rf = rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID);
11035 else if (rt2x00_rt(rt2x00dev, RT3352))
11037 else if (rt2x00_rt(rt2x00dev, RT3883))
11039 else if (rt2x00_rt(rt2x00dev, RT5350))
11041 else if (rt2x00_rt(rt2x00dev, RT5592))
11073 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
11078 rt2x00_set_rf(rt2x00dev, rf);
11083 rt2x00dev->default_ant.tx_chain_num =
11085 rt2x00dev->default_ant.rx_chain_num =
11088 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
11090 if (rt2x00_rt(rt2x00dev, RT3070) ||
11091 rt2x00_rt(rt2x00dev, RT3090) ||
11092 rt2x00_rt(rt2x00dev, RT3352) ||
11093 rt2x00_rt(rt2x00dev, RT3390)) {
11100 rt2x00dev->default_ant.tx = ANTENNA_A;
11101 rt2x00dev->default_ant.rx = ANTENNA_A;
11104 rt2x00dev->default_ant.tx = ANTENNA_A;
11105 rt2x00dev->default_ant.rx = ANTENNA_B;
11109 rt2x00dev->default_ant.tx = ANTENNA_A;
11110 rt2x00dev->default_ant.rx = ANTENNA_A;
11114 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R) ||
11115 rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5370G)) {
11116 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
11117 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
11124 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
11126 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
11132 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
11137 if (!rt2x00_rt(rt2x00dev, RT3352) &&
11139 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
11144 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
11145 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
11151 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
11152 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
11153 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
11155 rt2x00dev->led_mcu_reg = eeprom;
11161 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER);
11165 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
11170 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
11172 if (rt2x00_rt(rt2x00dev, RT3352) ||
11173 rt2x00_rt(rt2x00dev, RT6352)) {
11177 &rt2x00dev->cap_flags);
11181 &rt2x00dev->cap_flags);
11184 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF2);
11186 if (rt2x00_rt(rt2x00dev, RT6352) && eeprom != 0 && eeprom != 0xffff) {
11190 &rt2x00dev->cap_flags);
11192 &rt2x00dev->cap_flags);
11570 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
11572 struct hw_mode_spec *spec = &rt2x00dev->spec;
11583 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
11589 rt2x00dev->hw->wiphy->retry_short = 2;
11590 rt2x00dev->hw->wiphy->retry_long = 2;
11595 ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS);
11596 ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION);
11597 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
11598 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
11599 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
11608 if (!rt2x00_is_usb(rt2x00dev))
11609 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
11611 ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE);
11613 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
11614 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
11615 rt2800_eeprom_addr(rt2x00dev,
11627 rt2x00dev->hw->max_rates = 1;
11628 rt2x00dev->hw->max_report_rates = 7;
11629 rt2x00dev->hw->max_rate_tries = 1;
11636 switch (rt2x00dev->chip.rf) {
11665 if (rt2800_clk_is_20mhz(rt2x00dev))
11688 reg = rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX);
11709 if (!rt2x00_rf(rt2x00dev, RF2020))
11720 tx_chains = rt2x00dev->default_ant.tx_chain_num;
11721 rx_chains = rt2x00dev->default_ant.rx_chain_num;
11757 rt2x00dev->chan_survey =
11760 if (!rt2x00dev->chan_survey) {
11767 default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
11768 default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
11770 if (rt2x00dev->default_ant.tx_chain_num > 2)
11771 default_power3 = rt2800_eeprom_addr(rt2x00dev,
11784 default_power1 = rt2800_eeprom_addr(rt2x00dev,
11786 default_power2 = rt2800_eeprom_addr(rt2x00dev,
11789 if (rt2x00dev->default_ant.tx_chain_num > 2)
11791 rt2800_eeprom_addr(rt2x00dev,
11804 switch (rt2x00dev->chip.rf) {
11824 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
11831 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
11837 if (rt2x00_rt(rt2x00dev, RT3290))
11838 reg = rt2800_register_read(rt2x00dev, MAC_CSR0_3290);
11840 reg = rt2800_register_read(rt2x00dev, MAC_CSR0);
11864 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
11869 if (rt == RT5390 && rt2x00_is_soc(rt2x00dev))
11872 rt2x00_set_rt(rt2x00dev, rt, rev);
11877 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
11882 retval = rt2800_probe_rt(rt2x00dev);
11889 retval = rt2800_validate_eeprom(rt2x00dev);
11893 retval = rt2800_init_eeprom(rt2x00dev);
11901 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
11903 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
11908 retval = rt2800_probe_hw_mode(rt2x00dev);
11915 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
11916 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
11917 if (!rt2x00_is_usb(rt2x00dev))
11918 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
11923 if (!rt2x00_is_soc(rt2x00dev))
11924 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
11925 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
11926 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
11927 if (!rt2800_hwcrypt_disabled(rt2x00dev))
11928 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
11929 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
11930 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
11931 if (rt2x00_is_usb(rt2x00dev))
11932 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
11934 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
11935 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
11939 __set_bit(CAPABILITY_RESTART_HW, &rt2x00dev->cap_flags);
11940 rt2x00dev->link.watchdog_interval = msecs_to_jiffies(100);
11942 rt2x00dev->link.watchdog_disabled = true;
11948 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
11961 struct rt2x00_dev *rt2x00dev = hw->priv;
11969 rt2800_register_multiread(rt2x00dev, offset,
11979 struct rt2x00_dev *rt2x00dev = hw->priv;
11983 reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG);
11985 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
11987 reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG);
11989 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
11991 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
11993 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
11995 reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
11997 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
11999 reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
12001 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
12003 reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
12005 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
12007 reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
12009 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
12020 struct rt2x00_dev *rt2x00dev = hw->priv;
12044 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
12051 reg = rt2800_register_read(rt2x00dev, offset);
12053 rt2800_register_write(rt2x00dev, offset, reg);
12059 reg = rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG);
12061 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
12063 reg = rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG);
12065 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
12067 reg = rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG);
12069 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
12074 reg = rt2800_register_read(rt2x00dev, offset);
12079 rt2800_register_write(rt2x00dev, offset, reg);
12087 struct rt2x00_dev *rt2x00dev = hw->priv;
12091 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW1);
12093 reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW0);
12151 struct rt2x00_dev *rt2x00dev = hw->priv;
12153 &rt2x00dev->chan_survey[idx];
12156 if (idx >= rt2x00dev->bands[band].n_channels) {
12157 idx -= rt2x00dev->bands[band].n_channels;
12161 if (idx >= rt2x00dev->bands[band].n_channels)
12165 rt2800_update_survey(rt2x00dev);
12167 survey->channel = &rt2x00dev->bands[band].channels[idx];