Lines Matching refs:td
33 struct mt76_testmode_data *td = &phy->test;
36 struct sk_buff *skb = td->tx_skb;
41 if (!skb || !td->tx_pending)
47 tx_queued_limit = td->tx_queued_limit ? td->tx_queued_limit : 1000;
51 while (td->tx_pending > 0 &&
52 td->tx_queued - td->tx_done < tx_queued_limit &&
61 td->tx_pending--;
62 td->tx_queued++;
95 struct mt76_testmode_data *td = &phy->test;
97 dev_kfree_skb(td->tx_skb);
98 td->tx_skb = NULL;
106 struct mt76_testmode_data *td = &phy->test;
113 max_len = mt76_testmode_max_mpdu_len(phy, td->tx_rate_mode);
131 memcpy(hdr->addr1, td->addr[0], ETH_ALEN);
132 memcpy(hdr->addr2, td->addr[1], ETH_ALEN);
133 memcpy(hdr->addr3, td->addr[2], ETH_ALEN);
171 td->tx_skb = head;
180 struct mt76_testmode_data *td = &phy->test;
186 ret = mt76_testmode_alloc_skb(phy, td->tx_mpdu_len);
190 if (td->tx_rate_mode > MT76_TM_TX_MODE_VHT)
193 if (td->tx_antenna_mask)
194 max_nss = min_t(u8, max_nss, hweight8(td->tx_antenna_mask));
196 info = IEEE80211_SKB_CB(td->tx_skb);
199 rate->idx = td->tx_rate_idx;
201 switch (td->tx_rate_mode) {
230 if (td->tx_rate_nss > max_nss)
233 ieee80211_rate_set_vht(rate, td->tx_rate_idx, td->tx_rate_nss);
240 if (td->tx_rate_sgi)
243 if (td->tx_rate_ldpc)
246 if (td->tx_rate_stbc)
249 if (td->tx_rate_mode >= MT76_TM_TX_MODE_HT) {
272 struct mt76_testmode_data *td = &phy->test;
275 td->tx_queued = 0;
276 td->tx_done = 0;
277 td->tx_pending = td->tx_count;
284 struct mt76_testmode_data *td = &phy->test;
289 td->tx_pending = 0;
293 wait_event_timeout(dev->tx_wait, td->tx_done == td->tx_queued,
300 mt76_testmode_param_set(struct mt76_testmode_data *td, u16 idx)
302 td->param_set[idx / 32] |= BIT(idx % 32);
306 mt76_testmode_param_present(struct mt76_testmode_data *td, u16 idx)
308 return td->param_set[idx / 32] & BIT(idx % 32);
314 struct mt76_testmode_data *td = &phy->test;
316 if (td->tx_mpdu_len > 0)
319 td->tx_mpdu_len = 1024;
320 td->tx_count = 1;
321 td->tx_rate_mode = MT76_TM_TX_MODE_OFDM;
322 td->tx_rate_nss = 1;
324 memcpy(td->addr[0], phy->macaddr, ETH_ALEN);
325 memcpy(td->addr[1], phy->macaddr, ETH_ALEN);
326 memcpy(td->addr[2], phy->macaddr, ETH_ALEN);
366 struct mt76_testmode_data *td = &phy->test;
369 if (state == td->state && state == MT76_TM_STATE_OFF)
378 td->state != MT76_TM_STATE_IDLE) {
412 struct mt76_testmode_data *td = &phy->test;
432 memset(td, 0, sizeof(*td));
438 td->tx_count = nla_get_u32(tb[MT76_TM_ATTR_TX_COUNT]);
441 td->tx_rate_idx = nla_get_u8(tb[MT76_TM_ATTR_TX_RATE_IDX]);
443 if (mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_RATE_MODE], &td->tx_rate_mode,
445 mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_RATE_NSS], &td->tx_rate_nss,
447 mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_RATE_SGI], &td->tx_rate_sgi, 0, 2) ||
448 mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_RATE_LDPC], &td->tx_rate_ldpc, 0, 1) ||
449 mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_RATE_STBC], &td->tx_rate_stbc, 0, 1) ||
450 mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_LTF], &td->tx_ltf, 0, 2) ||
452 &td->tx_antenna_mask, 0, 0xff) ||
453 mt76_tm_get_u8(tb[MT76_TM_ATTR_TX_SPE_IDX], &td->tx_spe_idx, 0, 27) ||
455 &td->tx_duty_cycle, 0, 99) ||
457 &td->tx_power_control, 0, 1))
463 if (val > mt76_testmode_max_mpdu_len(phy, td->tx_rate_mode) ||
467 td->tx_mpdu_len = val;
471 td->tx_ipg = nla_get_u32(tb[MT76_TM_ATTR_TX_IPG]);
474 td->tx_time = nla_get_u32(tb[MT76_TM_ATTR_TX_TIME]);
477 td->freq_offset = nla_get_u32(tb[MT76_TM_ATTR_FREQ_OFFSET]);
484 state = td->state;
494 idx >= ARRAY_SIZE(td->tx_power))
497 td->tx_power[idx++] = nla_get_u8(cur);
510 memcpy(td->addr[idx], nla_data(cur), ETH_ALEN);
523 mt76_testmode_param_set(td, i);
539 struct mt76_testmode_data *td = &phy->test;
553 for (i = 0; i < ARRAY_SIZE(td->rx_stats.packets); i++) {
554 rx_packets += td->rx_stats.packets[i];
555 rx_fcs_error += td->rx_stats.fcs_error[i];
558 if (nla_put_u32(msg, MT76_TM_STATS_ATTR_TX_PENDING, td->tx_pending) ||
559 nla_put_u32(msg, MT76_TM_STATS_ATTR_TX_QUEUED, td->tx_queued) ||
560 nla_put_u32(msg, MT76_TM_STATS_ATTR_TX_DONE, td->tx_done) ||
575 struct mt76_testmode_data *td = &phy->test;
611 if (nla_put_u32(msg, MT76_TM_ATTR_STATE, td->state))
619 if (nla_put_u32(msg, MT76_TM_ATTR_TX_COUNT, td->tx_count) ||
620 nla_put_u32(msg, MT76_TM_ATTR_TX_LENGTH, td->tx_mpdu_len) ||
621 nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_MODE, td->tx_rate_mode) ||
622 nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_NSS, td->tx_rate_nss) ||
623 nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_IDX, td->tx_rate_idx) ||
624 nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_SGI, td->tx_rate_sgi) ||
625 nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_LDPC, td->tx_rate_ldpc) ||
626 nla_put_u8(msg, MT76_TM_ATTR_TX_RATE_STBC, td->tx_rate_stbc) ||
627 (mt76_testmode_param_present(td, MT76_TM_ATTR_TX_LTF) &&
628 nla_put_u8(msg, MT76_TM_ATTR_TX_LTF, td->tx_ltf)) ||
629 (mt76_testmode_param_present(td, MT76_TM_ATTR_TX_ANTENNA) &&
630 nla_put_u8(msg, MT76_TM_ATTR_TX_ANTENNA, td->tx_antenna_mask)) ||
631 (mt76_testmode_param_present(td, MT76_TM_ATTR_TX_SPE_IDX) &&
632 nla_put_u8(msg, MT76_TM_ATTR_TX_SPE_IDX, td->tx_spe_idx)) ||
633 (mt76_testmode_param_present(td, MT76_TM_ATTR_TX_DUTY_CYCLE) &&
634 nla_put_u8(msg, MT76_TM_ATTR_TX_DUTY_CYCLE, td->tx_duty_cycle)) ||
635 (mt76_testmode_param_present(td, MT76_TM_ATTR_TX_IPG) &&
636 nla_put_u32(msg, MT76_TM_ATTR_TX_IPG, td->tx_ipg)) ||
637 (mt76_testmode_param_present(td, MT76_TM_ATTR_TX_TIME) &&
638 nla_put_u32(msg, MT76_TM_ATTR_TX_TIME, td->tx_time)) ||
639 (mt76_testmode_param_present(td, MT76_TM_ATTR_TX_POWER_CONTROL) &&
640 nla_put_u8(msg, MT76_TM_ATTR_TX_POWER_CONTROL, td->tx_power_control)) ||
641 (mt76_testmode_param_present(td, MT76_TM_ATTR_FREQ_OFFSET) &&
642 nla_put_u8(msg, MT76_TM_ATTR_FREQ_OFFSET, td->freq_offset)))
645 if (mt76_testmode_param_present(td, MT76_TM_ATTR_TX_POWER)) {
650 for (i = 0; i < ARRAY_SIZE(td->tx_power); i++)
651 if (nla_put_u8(msg, i, td->tx_power[i]))
657 if (mt76_testmode_param_present(td, MT76_TM_ATTR_MAC_ADDRS)) {
663 if (nla_put(msg, i, ETH_ALEN, td->addr[i]))