Lines Matching refs:port
250 struct usb_tx_data_port *port;
267 port = &card->port[i];
268 if (context->ep == port->tx_data_ep) {
269 atomic_dec(&port->tx_data_urb_pending);
270 port->block_status = false;
347 struct usb_tx_data_port *port;
367 port = &card->port[i];
369 usb_kill_urb(port->tx_data_list[j].urb);
370 usb_free_urb(port->tx_data_list[j].urb);
371 port->tx_data_list[j].urb = NULL;
465 card->port[0].tx_data_ep = usb_endpoint_num(epd);
466 atomic_set(&card->port[0].tx_data_urb_pending, 0);
475 card->port[1].tx_data_ep = usb_endpoint_num(epd);
476 atomic_set(&card->port[1].tx_data_urb_pending, 0);
539 struct usb_tx_data_port *port;
582 port = &card->port[i];
584 if (port->tx_data_list[j].urb)
585 usb_kill_urb(port->tx_data_list[j].urb);
757 card->port[i].block_status = false;
777 if (active_port == card->port[i].tx_data_ep)
778 card->port[i].block_status = false;
780 card->port[i].block_status = true;
791 if (priv->usb_port == card->port[idx].tx_data_ep)
792 return !card->port[idx].block_status;
804 if (!card->port[i].block_status)
811 struct usb_tx_data_port *port, u8 ep,
841 atomic_inc(&port->tx_data_urb_pending);
844 atomic_read(&port->tx_data_urb_pending) ==
846 port->block_status = true;
857 atomic_dec(&port->tx_data_urb_pending);
858 port->block_status = false;
860 if (port->tx_data_ix)
861 port->tx_data_ix--;
863 port->tx_data_ix = MWIFIEX_TX_DATA_URB;
872 struct usb_tx_data_port *port,
884 if (port->tx_aggr.timer_cnxt.is_hold_timer_set) {
885 del_timer(&port->tx_aggr.timer_cnxt.hold_timer);
886 port->tx_aggr.timer_cnxt.is_hold_timer_set = false;
887 port->tx_aggr.timer_cnxt.hold_tmo_msecs = 0;
890 skb_aggr = mwifiex_alloc_dma_align_buf(port->tx_aggr.aggr_len,
896 while ((skb_tmp = skb_dequeue(&port->tx_aggr.aggr_list)))
899 port->tx_aggr.aggr_num = 0;
900 port->tx_aggr.aggr_len = 0;
907 while ((skb_tmp = skb_dequeue(&port->tx_aggr.aggr_list))) {
912 if (skb_queue_empty(&port->tx_aggr.aggr_list)) {
931 port->tx_aggr.aggr_num--;
932 port->tx_aggr.aggr_len -= (skb_tmp->len + pad);
940 port->tx_aggr.aggr_num = 0;
941 port->tx_aggr.aggr_len = 0;
959 struct usb_tx_data_port *port)
979 if (port->tx_aggr.aggr_len + skb->len + pad >
987 if (port->tx_aggr.aggr_len + skb->len + pad +
990 port->tx_aggr.aggr_num + 2 >
1000 if (port->tx_aggr.aggr_num > 0) {
1002 if (port->tx_aggr.aggr_len + skb->len + pad >
1025 if (skb_queue_empty(&port->tx_aggr.aggr_list)) {
1039 skb_queue_tail(&port->tx_aggr.aggr_list, skb);
1040 port->tx_aggr.aggr_len += (skb->len + pad);
1041 port->tx_aggr.aggr_num++;
1050 if (!port->tx_aggr.timer_cnxt.is_hold_timer_set) {
1051 port->tx_aggr.timer_cnxt.hold_tmo_msecs =
1054 port->tx_aggr.timer_cnxt.hold_tmo_msecs;
1055 mod_timer(&port->tx_aggr.timer_cnxt.hold_timer,
1057 port->tx_aggr.timer_cnxt.is_hold_timer_set = true;
1059 if (port->tx_aggr.timer_cnxt.hold_tmo_msecs <
1063 ++port->tx_aggr.timer_cnxt.hold_tmo_msecs;
1064 mod_timer(&port->tx_aggr.timer_cnxt.hold_timer,
1072 ret = mwifiex_usb_prepare_tx_aggr_skb(adapter, port, &skb_send);
1074 context = &port->tx_data_list[port->tx_data_ix++];
1075 ret = mwifiex_usb_construct_send_urb(adapter, port, ep,
1085 if (atomic_read(&port->tx_data_urb_pending) >=
1087 port->block_status = true;
1095 if (port->tx_data_ix >= MWIFIEX_TX_DATA_URB)
1096 port->tx_data_ix = 0;
1104 context = &port->tx_data_list[port->tx_data_ix++];
1105 return mwifiex_usb_construct_send_urb(adapter, port, ep,
1111 skb_queue_tail(&port->tx_aggr.aggr_list, skb);
1112 port->tx_aggr.aggr_len += (skb->len + pad);
1113 port->tx_aggr.aggr_num++;
1115 if (!port->tx_aggr.timer_cnxt.is_hold_timer_set) {
1116 port->tx_aggr.timer_cnxt.hold_tmo_msecs =
1118 timeout = port->tx_aggr.timer_cnxt.hold_tmo_msecs;
1119 mod_timer(&port->tx_aggr.timer_cnxt.hold_timer,
1121 port->tx_aggr.timer_cnxt.is_hold_timer_set = true;
1135 struct usb_tx_data_port *port = timer_context->port;
1138 spin_lock_bh(&port->tx_aggr_lock);
1139 err = mwifiex_usb_prepare_tx_aggr_skb(adapter, port, &skb_send);
1146 if (atomic_read(&port->tx_data_urb_pending) >=
1148 port->block_status = true;
1155 if (port->tx_data_ix >= MWIFIEX_TX_DATA_URB)
1156 port->tx_data_ix = 0;
1158 urb_cnxt = &port->tx_data_list[port->tx_data_ix++];
1159 err = mwifiex_usb_construct_send_urb(adapter, port, port->tx_data_ep,
1165 spin_unlock_bh(&port->tx_aggr_lock);
1175 struct usb_tx_data_port *port = NULL;
1194 /* get the data port structure for endpoint */
1196 if (ep == card->port[idx].tx_data_ep) {
1197 port = &card->port[idx];
1198 if (atomic_read(&port->tx_data_urb_pending)
1200 port->block_status = true;
1205 if (port->tx_data_ix >= MWIFIEX_TX_DATA_URB)
1206 port->tx_data_ix = 0;
1211 if (!port) {
1212 mwifiex_dbg(adapter, ERROR, "Wrong usb tx data port\n");
1217 spin_lock_bh(&port->tx_aggr_lock);
1219 tx_param, port);
1220 spin_unlock_bh(&port->tx_aggr_lock);
1224 context = &port->tx_data_list[port->tx_data_ix++];
1227 return mwifiex_usb_construct_send_urb(adapter, port, ep, context, skb);
1233 struct usb_tx_data_port *port;
1244 port = &card->port[i];
1245 if (!port->tx_data_ep)
1247 port->tx_data_ix = 0;
1248 skb_queue_head_init(&port->tx_aggr.aggr_list);
1249 if (port->tx_data_ep == MWIFIEX_USB_EP_DATA)
1250 port->block_status = false;
1252 port->block_status = true;
1254 port->tx_data_list[j].adapter = adapter;
1255 port->tx_data_list[j].ep = port->tx_data_ep;
1256 port->tx_data_list[j].urb =
1258 if (!port->tx_data_list[j].urb)
1262 port->tx_aggr.timer_cnxt.adapter = adapter;
1263 port->tx_aggr.timer_cnxt.port = port;
1264 port->tx_aggr.timer_cnxt.is_hold_timer_set = false;
1265 port->tx_aggr.timer_cnxt.hold_tmo_msecs = 0;
1266 timer_setup(&port->tx_aggr.timer_cnxt.hold_timer,
1350 struct usb_tx_data_port *port;
1355 port = &card->port[idx];
1358 skb_dequeue(&port->tx_aggr.aggr_list)))
1361 if (port->tx_aggr.timer_cnxt.hold_timer.function)
1362 del_timer_sync(&port->tx_aggr.timer_cnxt.hold_timer);
1363 port->tx_aggr.timer_cnxt.is_hold_timer_set = false;
1364 port->tx_aggr.timer_cnxt.hold_tmo_msecs = 0;