Lines Matching refs:dbg
8 #include "iwl-dbg-tlv.h"
9 #include "fw/dbg.h"
115 return iwl_dbg_tlv_add(tlv, &trans->dbg.debug_info_tlv_list);
153 trans->dbg.fw_mon_cfg[alloc_id] = *alloc;
184 return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].hcmd_list);
228 trans->dbg.imr_data.sram_addr =
230 trans->dbg.imr_data.sram_size =
235 active_reg = &trans->dbg.active_regions[id];
275 trans->dbg.last_tp_resetfw = 0xFF;
286 ret = iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].trig_list);
313 return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].config_list);
330 &trans->dbg.external_ini_cfg : &trans->dbg.internal_ini_cfg;
345 !(domain & trans->dbg.domains_bitmap)) {
348 domain, trans->dbg.domains_bitmap);
382 struct list_head *timer_list = &trans->dbg.periodic_trig_list;
403 fw_mon = &trans->dbg.fw_mon_ini[alloc_id];
428 for (i = 0; i < ARRAY_SIZE(trans->dbg.active_regions); i++) {
430 &trans->dbg.active_regions[i];
437 &trans->dbg.debug_info_tlv_list, list) {
442 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) {
444 &trans->dbg.time_point[i];
472 for (i = 0; i < ARRAY_SIZE(trans->dbg.fw_mon_ini); i++)
527 INIT_LIST_HEAD(&trans->dbg.debug_info_tlv_list);
528 INIT_LIST_HEAD(&trans->dbg.periodic_trig_list);
530 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) {
532 &trans->dbg.time_point[i];
592 fw_mon_cfg = &fwrt->trans->dbg.fw_mon_cfg[alloc_id];
593 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
669 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) !=
673 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
751 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) !=
758 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
798 &fwrt->trans->dbg.fw_mon_ini[IWL_FW_INI_ALLOCATION_ID_DBGC1].frags[0];
814 if (fwrt->trans->dbg.fw_mon_cfg[i].buf_location ==
902 struct iwl_dram_data *frags = &fwrt->trans->dbg.fw_mon_ini[1].frags[0];
941 fwrt->trans->dbg.ucode_preset = debug_token_config;
975 &fwrt->trans->dbg.time_point[IWL_FW_INI_TIME_POINT_PERIODIC].active_trig_list;
1018 &fwrt->trans->dbg.periodic_trig_list);
1241 fwrt->trans->dbg.restart_required = FALSE;
1246 fwrt->trans->dbg.restart_required,
1247 fwrt->trans->dbg.last_tp_resetfw);
1251 fwrt->trans->dbg.restart_required = TRUE;
1253 fwrt->trans->dbg.last_tp_resetfw ==
1255 fwrt->trans->dbg.restart_required = FALSE;
1256 fwrt->trans->dbg.last_tp_resetfw = 0xFF;
1261 fwrt->trans->dbg.restart_required = TRUE;
1266 fwrt->trans->dbg.restart_required = FALSE;
1267 fwrt->trans->dbg.last_tp_resetfw =
1283 enum iwl_fw_ini_buffer_location *ini_dest = &fwrt->trans->dbg.ini_dest;
1290 fwrt->trans->dbg.domains_bitmap);
1292 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.time_point); i++) {
1294 &fwrt->trans->dbg.time_point[i];
1309 &fwrt->trans->dbg.fw_mon_cfg[i];
1336 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions) && failed_alloc; i++) {
1339 &fwrt->trans->dbg.active_regions[i];
1343 fwrt->trans->dbg.unsupported_region_msk |= BIT(i);
1359 fwrt->trans->dbg.unsupported_region_msk |= BIT(i);
1378 hcmd_list = &fwrt->trans->dbg.time_point[tp_id].hcmd_list;
1379 trig_list = &fwrt->trans->dbg.time_point[tp_id].active_trig_list;
1380 conf_list = &fwrt->trans->dbg.time_point[tp_id].config_list;