Lines Matching defs:trans
7 #include "iwl-trans.h"
98 static int iwl_dbg_tlv_alloc_debug_info(struct iwl_trans *trans,
112 IWL_DEBUG_FW(trans, "WRT: Loading debug cfg: %s\n",
115 return iwl_dbg_tlv_add(tlv, &trans->dbg.debug_info_tlv_list);
118 static int iwl_dbg_tlv_alloc_buf_alloc(struct iwl_trans *trans,
149 IWL_ERR(trans, "WRT: Invalid DRAM buffer allocation requested size (0)\n");
153 trans->dbg.fw_mon_cfg[alloc_id] = *alloc;
157 IWL_ERR(trans,
163 static int iwl_dbg_tlv_alloc_hcmd(struct iwl_trans *trans,
178 IWL_ERR(trans,
184 return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].hcmd_list);
187 static int iwl_dbg_tlv_alloc_region(struct iwl_trans *trans,
207 IWL_DEBUG_FW(trans, "WRT: parsing region: %.*s\n",
211 IWL_ERR(trans, "WRT: Invalid region id %u\n", id);
217 IWL_ERR(trans, "WRT: Invalid region type %u\n", type);
222 !trans->ops->read_config32) {
223 IWL_ERR(trans, "WRT: Unsupported region type %u\n", type);
228 trans->dbg.imr_data.sram_addr =
230 trans->dbg.imr_data.sram_size =
235 active_reg = &trans->dbg.active_regions[id];
237 IWL_WARN(trans, "WRT: Overriding region id %u\n", id);
246 IWL_DEBUG_FW(trans, "WRT: Enabling region id %u type %u\n", id, type);
251 static int iwl_dbg_tlv_alloc_trigger(struct iwl_trans *trans,
266 IWL_ERR(trans,
272 IWL_DEBUG_FW(trans,
275 trans->dbg.last_tp_resetfw = 0xFF;
286 ret = iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].trig_list);
292 static int iwl_dbg_tlv_config_set(struct iwl_trans *trans,
301 IWL_DEBUG_FW(trans,
308 IWL_DEBUG_FW(trans,
313 return iwl_dbg_tlv_add(tlv, &trans->dbg.time_point[tp].config_list);
316 static int (*dbg_tlv_alloc[])(struct iwl_trans *trans,
326 void iwl_dbg_tlv_alloc(struct iwl_trans *trans, const struct iwl_ucode_tlv *tlv,
330 &trans->dbg.external_ini_cfg : &trans->dbg.internal_ini_cfg;
345 !(domain & trans->dbg.domains_bitmap)) {
346 IWL_DEBUG_FW(trans,
348 domain, trans->dbg.domains_bitmap);
353 IWL_ERR(trans, "WRT: Unsupported TLV type 0x%x\n", type);
358 IWL_ERR(trans, "WRT: Unsupported TLV 0x%x version %u\n", type,
363 ret = dbg_tlv_alloc[tlv_idx](trans, tlv);
365 IWL_WARN(trans,
380 void iwl_dbg_tlv_del_timers(struct iwl_trans *trans)
382 struct list_head *timer_list = &trans->dbg.periodic_trig_list;
393 static void iwl_dbg_tlv_fragments_free(struct iwl_trans *trans,
403 fw_mon = &trans->dbg.fw_mon_ini[alloc_id];
408 dma_free_coherent(trans->dev, frag->size, frag->block,
421 void iwl_dbg_tlv_free(struct iwl_trans *trans)
426 iwl_dbg_tlv_del_timers(trans);
428 for (i = 0; i < ARRAY_SIZE(trans->dbg.active_regions); i++) {
430 &trans->dbg.active_regions[i];
437 &trans->dbg.debug_info_tlv_list, list) {
442 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) {
444 &trans->dbg.time_point[i];
472 for (i = 0; i < ARRAY_SIZE(trans->dbg.fw_mon_ini); i++)
473 iwl_dbg_tlv_fragments_free(trans, i);
476 static int iwl_dbg_tlv_parse_bin(struct iwl_trans *trans, const u8 *data,
489 IWL_ERR(trans, "invalid TLV len: %zd/%u\n",
496 iwl_dbg_tlv_alloc(trans, tlv, true);
502 void iwl_dbg_tlv_load_bin(struct device *dev, struct iwl_trans *trans)
509 trans->trans_cfg->device_family <= IWL_DEVICE_FAMILY_8000)
513 IWL_DEBUG_FW(trans, "%s %s\n", res ? "didn't load" : "loaded", yoyo_bin);
518 iwl_dbg_tlv_parse_bin(trans, fw->data, fw->size);
523 void iwl_dbg_tlv_init(struct iwl_trans *trans)
527 INIT_LIST_HEAD(&trans->dbg.debug_info_tlv_list);
528 INIT_LIST_HEAD(&trans->dbg.periodic_trig_list);
530 for (i = 0; i < ARRAY_SIZE(trans->dbg.time_point); i++) {
532 &trans->dbg.time_point[i];
592 fw_mon_cfg = &fwrt->trans->dbg.fw_mon_cfg[alloc_id];
593 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
607 if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) {
611 } else if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_BZ &&
640 iwl_dbg_tlv_fragments_free(fwrt->trans,
669 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) !=
673 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
715 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd);
751 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) !=
758 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
798 &fwrt->trans->dbg.fw_mon_ini[IWL_FW_INI_ALLOCATION_ID_DBGC1].frags[0];
814 if (fwrt->trans->dbg.fw_mon_cfg[i].buf_location ==
848 iwl_trans_send_cmd(fwrt->trans, &cmd);
866 if (!iwl_trans_grab_nic_access(fwrt->trans)) {
875 iwl_trans_write_prph(fwrt->trans, address + offset, value);
877 iwl_trans_release_nic_access(fwrt->trans);
884 iwl_trans_write_mem32(fwrt->trans, address + offset, value);
894 iwl_write32(fwrt->trans, address + offset, value);
902 struct iwl_dram_data *frags = &fwrt->trans->dbg.fw_mon_ini[1].frags[0];
926 ret = iwl_trans_write_mem(fwrt->trans,
941 fwrt->trans->dbg.ucode_preset = debug_token_config;
975 &fwrt->trans->dbg.time_point[IWL_FW_INI_TIME_POINT_PERIODIC].active_trig_list;
1018 &fwrt->trans->dbg.periodic_trig_list);
1241 fwrt->trans->dbg.restart_required = FALSE;
1246 fwrt->trans->dbg.restart_required,
1247 fwrt->trans->dbg.last_tp_resetfw);
1249 if (fwrt->trans->trans_cfg->device_family ==
1251 fwrt->trans->dbg.restart_required = TRUE;
1253 fwrt->trans->dbg.last_tp_resetfw ==
1255 fwrt->trans->dbg.restart_required = FALSE;
1256 fwrt->trans->dbg.last_tp_resetfw = 0xFF;
1261 fwrt->trans->dbg.restart_required = TRUE;
1266 fwrt->trans->dbg.restart_required = FALSE;
1267 fwrt->trans->dbg.last_tp_resetfw =
1283 enum iwl_fw_ini_buffer_location *ini_dest = &fwrt->trans->dbg.ini_dest;
1290 fwrt->trans->dbg.domains_bitmap);
1292 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.time_point); i++) {
1294 &fwrt->trans->dbg.time_point[i];
1309 &fwrt->trans->dbg.fw_mon_cfg[i];
1336 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions) && failed_alloc; i++) {
1339 &fwrt->trans->dbg.active_regions[i];
1343 fwrt->trans->dbg.unsupported_region_msk |= BIT(i);
1359 fwrt->trans->dbg.unsupported_region_msk |= BIT(i);
1373 if (!iwl_trans_dbg_ini_valid(fwrt->trans) ||
1378 hcmd_list = &fwrt->trans->dbg.time_point[tp_id].hcmd_list;
1379 trig_list = &fwrt->trans->dbg.time_point[tp_id].active_trig_list;
1380 conf_list = &fwrt->trans->dbg.time_point[tp_id].config_list;