Lines Matching defs:fwrt
47 * @fwrt: &struct iwl_fw_runtime
53 struct iwl_fw_runtime *fwrt;
541 static int iwl_dbg_tlv_alloc_fragment(struct iwl_fw_runtime *fwrt,
558 block = dma_alloc_coherent(fwrt->dev, pages * PAGE_SIZE,
564 IWL_WARN(fwrt, "WRT: Failed to allocate fragment size %lu\n",
580 static int iwl_dbg_tlv_alloc_fragments(struct iwl_fw_runtime *fwrt,
592 fw_mon_cfg = &fwrt->trans->dbg.fw_mon_cfg[alloc_id];
593 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
607 if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) {
611 } else if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_BZ &&
629 IWL_DEBUG_FW(fwrt,
633 pages = iwl_dbg_tlv_alloc_fragment(fwrt, &fw_mon->frags[i],
640 iwl_dbg_tlv_fragments_free(fwrt->trans,
654 static int iwl_dbg_tlv_apply_buffer(struct iwl_fw_runtime *fwrt,
661 if (!fw_has_capa(&fwrt->fw->ucode_capa,
669 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) !=
673 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
687 IWL_DEBUG_FW(fwrt, "WRT: Applying DRAM destination (alloc_id=%u)\n",
715 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd);
725 static void iwl_dbg_tlv_apply_buffers(struct iwl_fw_runtime *fwrt)
729 if (fw_has_capa(&fwrt->fw->ucode_capa,
734 ret = iwl_dbg_tlv_apply_buffer(fwrt, i);
736 IWL_WARN(fwrt,
742 static int iwl_dbg_tlv_update_dram(struct iwl_fw_runtime *fwrt,
751 if (le32_to_cpu(fwrt->trans->dbg.fw_mon_cfg[alloc_id].buf_location) !=
753 IWL_DEBUG_FW(fwrt, "WRT: alloc_id %u location is not in DRAM_PATH\n",
758 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id];
776 IWL_DEBUG_FW(fwrt, "WRT: DRAM buffer details alloc_id=%u, num_frags=%u\n",
785 IWL_DEBUG_FW(fwrt, "WRT: DRAM fragment details\n");
786 IWL_DEBUG_FW(fwrt, "frag=%u, addr=0x%016llx, size=0x%x)\n",
793 static void iwl_dbg_tlv_update_drams(struct iwl_fw_runtime *fwrt)
798 &fwrt->trans->dbg.fw_mon_ini[IWL_FW_INI_ALLOCATION_ID_DBGC1].frags[0];
806 if (!fw_has_capa(&fwrt->fw->ucode_capa,
814 if (fwrt->trans->dbg.fw_mon_cfg[i].buf_location ==
818 ret = iwl_dbg_tlv_update_dram(fwrt, i, dram_info);
822 IWL_INFO(fwrt,
833 static void iwl_dbg_tlv_send_hcmds(struct iwl_fw_runtime *fwrt,
848 iwl_trans_send_cmd(fwrt->trans, &cmd);
852 static void iwl_dbg_tlv_apply_config(struct iwl_fw_runtime *fwrt,
866 if (!iwl_trans_grab_nic_access(fwrt->trans)) {
867 IWL_DEBUG_FW(fwrt, "WRT: failed to get nic access\n");
868 IWL_DEBUG_FW(fwrt, "WRT: skipping MAC PERIPHERY config\n");
871 IWL_DEBUG_FW(fwrt, "WRT: MAC PERIPHERY config len: len %u\n", len);
875 iwl_trans_write_prph(fwrt->trans, address + offset, value);
877 iwl_trans_release_nic_access(fwrt->trans);
884 iwl_trans_write_mem32(fwrt->trans, address + offset, value);
885 IWL_DEBUG_FW(fwrt, "WRT: DEV_MEM: count %u, add: %u val: %u\n",
894 iwl_write32(fwrt->trans, address + offset, value);
895 IWL_DEBUG_FW(fwrt, "WRT: CSR: count %u, add: %u val: %u\n",
902 struct iwl_dram_data *frags = &fwrt->trans->dbg.fw_mon_ini[1].frags[0];
915 IWL_DEBUG_FW(fwrt, "WRT: dram_base_addr 0x%016llx, dram_size 0x%x\n",
917 IWL_DEBUG_FW(fwrt, "WRT: config_list->addr_offset: %u\n",
926 ret = iwl_trans_write_mem(fwrt->trans,
929 IWL_ERR(fwrt, "Failed to write dram_info to HW_SMEM\n");
939 IWL_DEBUG_FW(fwrt, "WRT: Setting HWM debug token config: %u\n",
941 fwrt->trans->dbg.ucode_preset = debug_token_config;
959 ret = iwl_fw_dbg_ini_collect(timer_node->fwrt, &dump_data, false);
971 static void iwl_dbg_tlv_set_periodic_trigs(struct iwl_fw_runtime *fwrt)
975 &fwrt->trans->dbg.time_point[IWL_FW_INI_TIME_POINT_PERIODIC].active_trig_list;
991 IWL_ERR(fwrt,
997 IWL_WARN(fwrt,
1007 IWL_ERR(fwrt,
1012 timer_node->fwrt = fwrt;
1018 &fwrt->trans->dbg.periodic_trig_list);
1020 IWL_DEBUG_FW(fwrt, "WRT: Enabling periodic trigger\n");
1053 static int iwl_dbg_tlv_override_trig_node(struct iwl_fw_runtime *fwrt,
1069 IWL_DEBUG_FW(fwrt,
1076 IWL_DEBUG_FW(fwrt,
1089 IWL_WARN(fwrt,
1107 IWL_DEBUG_FW(fwrt,
1116 IWL_DEBUG_FW(fwrt,
1122 IWL_DEBUG_FW(fwrt,
1133 iwl_dbg_tlv_add_active_trigger(struct iwl_fw_runtime *fwrt,
1153 IWL_DEBUG_FW(fwrt, "WRT: Enabling trigger (time point %u)\n",
1158 return iwl_dbg_tlv_override_trig_node(fwrt, trig_tlv, match);
1162 iwl_dbg_tlv_gen_active_trig_list(struct iwl_fw_runtime *fwrt,
1172 iwl_dbg_tlv_add_active_trigger(fwrt, active_trig_list, tlv);
1176 static bool iwl_dbg_tlv_check_fw_pkt(struct iwl_fw_runtime *fwrt,
1203 iwl_dbg_tlv_tp_trigger(struct iwl_fw_runtime *fwrt, bool sync,
1206 bool (*data_check)(struct iwl_fw_runtime *fwrt,
1224 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data, sync);
1231 data_check(fwrt, &dump_data, tp_data,
1233 ret = iwl_fw_dbg_ini_collect(fwrt, &dump_data, sync);
1241 fwrt->trans->dbg.restart_required = FALSE;
1242 IWL_DEBUG_FW(fwrt, "WRT: tp %d, reset_fw %d\n",
1244 IWL_DEBUG_FW(fwrt,
1246 fwrt->trans->dbg.restart_required,
1247 fwrt->trans->dbg.last_tp_resetfw);
1249 if (fwrt->trans->trans_cfg->device_family ==
1251 fwrt->trans->dbg.restart_required = TRUE;
1253 fwrt->trans->dbg.last_tp_resetfw ==
1255 fwrt->trans->dbg.restart_required = FALSE;
1256 fwrt->trans->dbg.last_tp_resetfw = 0xFF;
1257 IWL_DEBUG_FW(fwrt, "WRT: FW_ASSERT due to reset_fw_mode-no restart\n");
1260 IWL_DEBUG_FW(fwrt, "WRT: stop and reload firmware\n");
1261 fwrt->trans->dbg.restart_required = TRUE;
1264 IWL_DEBUG_FW(fwrt,
1266 fwrt->trans->dbg.restart_required = FALSE;
1267 fwrt->trans->dbg.last_tp_resetfw =
1271 IWL_DEBUG_FW(fwrt,
1274 IWL_ERR(fwrt, "WRT: wrong resetfw %d\n",
1281 static void iwl_dbg_tlv_init_cfg(struct iwl_fw_runtime *fwrt)
1283 enum iwl_fw_ini_buffer_location *ini_dest = &fwrt->trans->dbg.ini_dest;
1288 IWL_DEBUG_FW(fwrt,
1290 fwrt->trans->dbg.domains_bitmap);
1292 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.time_point); i++) {
1294 &fwrt->trans->dbg.time_point[i];
1296 iwl_dbg_tlv_gen_active_trig_list(fwrt, tp);
1309 &fwrt->trans->dbg.fw_mon_cfg[i];
1323 ret = iwl_dbg_tlv_alloc_fragments(fwrt, i);
1326 IWL_WARN(fwrt,
1336 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions) && failed_alloc; i++) {
1339 &fwrt->trans->dbg.active_regions[i];
1343 fwrt->trans->dbg.unsupported_region_msk |= BIT(i);
1354 IWL_DEBUG_FW(fwrt,
1359 fwrt->trans->dbg.unsupported_region_msk |= BIT(i);
1366 void _iwl_dbg_tlv_time_point(struct iwl_fw_runtime *fwrt,
1373 if (!iwl_trans_dbg_ini_valid(fwrt->trans) ||
1378 hcmd_list = &fwrt->trans->dbg.time_point[tp_id].hcmd_list;
1379 trig_list = &fwrt->trans->dbg.time_point[tp_id].active_trig_list;
1380 conf_list = &fwrt->trans->dbg.time_point[tp_id].config_list;
1384 iwl_dbg_tlv_init_cfg(fwrt);
1385 iwl_dbg_tlv_apply_config(fwrt, conf_list);
1386 iwl_dbg_tlv_update_drams(fwrt);
1387 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL);
1390 iwl_dbg_tlv_apply_buffers(fwrt);
1391 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1392 iwl_dbg_tlv_apply_config(fwrt, conf_list);
1393 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL);
1396 iwl_dbg_tlv_set_periodic_trigs(fwrt);
1397 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1402 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1403 iwl_dbg_tlv_apply_config(fwrt, conf_list);
1404 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data,
1408 iwl_dbg_tlv_send_hcmds(fwrt, hcmd_list);
1409 iwl_dbg_tlv_apply_config(fwrt, conf_list);
1410 iwl_dbg_tlv_tp_trigger(fwrt, sync, trig_list, tp_data, NULL);