Lines Matching defs:read
290 /* alias for 32-bit indirect read (for SRAM/reg above 4K), with debug wrapper */
294 /* alias for 8-bit indirect read (for SRAM/reg above 4K), with debug wrapper */
367 /* 8-bit direct read (low 4K) */
373 /* alias to 8-bit direct read (low 4K of SRAM/regs), with debug wrapper */
380 /* 32-bit direct read (low 4K) */
386 /* alias to 32-bit direct read (low 4K of SRAM/regs), with debug wrapper */
394 /* alias to multi-byte read (SRAM/regs above 4K), with debug wrapper */
401 /* alias to multi-byte read (SRAM/regs above 4K), with debug wrapper */
440 /* 8-bit indirect read (above 4K) */
450 /* 32-bit indirect read (above 4K) */
463 /* General purpose, no alignment requirement, iterative (multi-byte) read, */
686 * read from the table
2554 * device driver has read access to the EEPROM by way of indirect addressing
2562 * select and why do have to keep driving the eeprom clock?), read
2656 /* read entire contents of eeprom into private buffer */
3409 rxq->read = rxq->write = 0;
3586 /* read eeprom data */
3598 ipw_write32(priv, IPW_RX_READ_INDEX, priv->rxq->read);
3655 int s = q->read - q->write;
3686 * @param read_register Address for 'read' register
3696 int count, u32 read, u32 write, u32 base, u32 size)
3709 q->reg_r = read;
3714 ipw_write32(priv, read, 0);
3722 int count, u32 read, u32 write, u32 base, u32 size)
3741 ipw_queue_init(priv, &q->q, count, read, write, base, size);
5030 * to -- the driver can read up to (but not including) this position and get
5034 * The WRITE index maps to the last position the driver has read from -- the
5052 * + In ipw_rx_queue_replenish (scheduled) if 'processed' != 'read' then the
5054 * 'processed' and 'read' driver indexes as well)
5219 rxq->read = rxq->write = 0;
8210 i = priv->rxq->read;
8385 priv->rxq->read = i;
8391 priv->rxq->read = i;