Lines Matching refs:wcn
30 static void wcn36xx_ccu_write_register(struct wcn36xx *wcn, int addr, int data)
36 writel(data, wcn->ccu_base + addr);
39 static void wcn36xx_dxe_write_register(struct wcn36xx *wcn, int addr, int data)
45 writel(data, wcn->dxe_base + addr);
48 static void wcn36xx_dxe_read_register(struct wcn36xx *wcn, int addr, int *data)
50 *data = readl(wcn->dxe_base + addr);
101 int wcn36xx_dxe_alloc_ctl_blks(struct wcn36xx *wcn)
105 wcn->dxe_tx_l_ch.ch_type = WCN36XX_DXE_CH_TX_L;
106 wcn->dxe_tx_h_ch.ch_type = WCN36XX_DXE_CH_TX_H;
107 wcn->dxe_rx_l_ch.ch_type = WCN36XX_DXE_CH_RX_L;
108 wcn->dxe_rx_h_ch.ch_type = WCN36XX_DXE_CH_RX_H;
110 wcn->dxe_tx_l_ch.desc_num = WCN36XX_DXE_CH_DESC_NUMB_TX_L;
111 wcn->dxe_tx_h_ch.desc_num = WCN36XX_DXE_CH_DESC_NUMB_TX_H;
112 wcn->dxe_rx_l_ch.desc_num = WCN36XX_DXE_CH_DESC_NUMB_RX_L;
113 wcn->dxe_rx_h_ch.desc_num = WCN36XX_DXE_CH_DESC_NUMB_RX_H;
115 wcn->dxe_tx_l_ch.dxe_wq = WCN36XX_DXE_WQ_TX_L(wcn);
116 wcn->dxe_tx_h_ch.dxe_wq = WCN36XX_DXE_WQ_TX_H(wcn);
118 wcn->dxe_tx_l_ch.ctrl_bd = WCN36XX_DXE_CTRL_TX_L_BD;
119 wcn->dxe_tx_h_ch.ctrl_bd = WCN36XX_DXE_CTRL_TX_H_BD;
121 wcn->dxe_tx_l_ch.ctrl_skb = WCN36XX_DXE_CTRL_TX_L_SKB;
122 wcn->dxe_tx_h_ch.ctrl_skb = WCN36XX_DXE_CTRL_TX_H_SKB;
124 wcn->dxe_tx_l_ch.reg_ctrl = WCN36XX_DXE_REG_CTL_TX_L;
125 wcn->dxe_tx_h_ch.reg_ctrl = WCN36XX_DXE_REG_CTL_TX_H;
127 wcn->dxe_tx_l_ch.def_ctrl = WCN36XX_DXE_CH_DEFAULT_CTL_TX_L;
128 wcn->dxe_tx_h_ch.def_ctrl = WCN36XX_DXE_CH_DEFAULT_CTL_TX_H;
131 ret = wcn36xx_dxe_allocate_ctl_block(&wcn->dxe_tx_l_ch);
134 ret = wcn36xx_dxe_allocate_ctl_block(&wcn->dxe_tx_h_ch);
137 ret = wcn36xx_dxe_allocate_ctl_block(&wcn->dxe_rx_l_ch);
140 ret = wcn36xx_dxe_allocate_ctl_block(&wcn->dxe_rx_h_ch);
145 ret = qcom_smem_state_update_bits(wcn->tx_enable_state,
156 wcn36xx_dxe_free_ctl_blks(wcn);
160 void wcn36xx_dxe_free_ctl_blks(struct wcn36xx *wcn)
162 wcn36xx_dxe_free_ctl_block(&wcn->dxe_tx_l_ch);
163 wcn36xx_dxe_free_ctl_block(&wcn->dxe_tx_h_ch);
164 wcn36xx_dxe_free_ctl_block(&wcn->dxe_rx_l_ch);
165 wcn36xx_dxe_free_ctl_block(&wcn->dxe_rx_h_ch);
168 static int wcn36xx_dxe_init_descs(struct wcn36xx *wcn, struct wcn36xx_dxe_ch *wcn_ch)
170 struct device *dev = wcn->dev;
194 cur_dxe->dst_addr_l = WCN36XX_DXE_WQ_TX_L(wcn);
198 cur_dxe->dst_addr_l = WCN36XX_DXE_WQ_TX_H(wcn);
260 static int wcn36xx_dxe_enable_ch_int(struct wcn36xx *wcn, u16 wcn_ch)
264 wcn36xx_dxe_read_register(wcn,
270 wcn36xx_dxe_write_register(wcn,
276 static void wcn36xx_dxe_disable_ch_int(struct wcn36xx *wcn, u16 wcn_ch)
280 wcn36xx_dxe_read_register(wcn,
286 wcn36xx_dxe_write_register(wcn,
316 static int wcn36xx_dxe_ch_alloc_skb(struct wcn36xx *wcn,
325 wcn36xx_dxe_fill_skb(wcn->dev, cur_ctl, GFP_KERNEL);
332 static void wcn36xx_dxe_ch_free_skbs(struct wcn36xx *wcn,
344 void wcn36xx_dxe_tx_ack_ind(struct wcn36xx *wcn, u32 status)
350 spin_lock_irqsave(&wcn->dxe_lock, flags);
351 skb = wcn->tx_ack_skb;
352 wcn->tx_ack_skb = NULL;
353 del_timer(&wcn->tx_ack_timer);
354 spin_unlock_irqrestore(&wcn->dxe_lock, flags);
370 ieee80211_tx_status_irqsafe(wcn->hw, skb);
371 ieee80211_wake_queues(wcn->hw);
376 struct wcn36xx *wcn = from_timer(wcn, t, tx_ack_timer);
384 spin_lock_irqsave(&wcn->dxe_lock, flags);
385 skb = wcn->tx_ack_skb;
386 wcn->tx_ack_skb = NULL;
387 spin_unlock_irqrestore(&wcn->dxe_lock, flags);
396 ieee80211_tx_status_irqsafe(wcn->hw, skb);
397 ieee80211_wake_queues(wcn->hw);
400 static void reap_tx_dxes(struct wcn36xx *wcn, struct wcn36xx_dxe_ch *ch)
419 dma_unmap_single(wcn->dev, ctl->desc->src_addr_l,
425 ieee80211_tx_status_irqsafe(wcn->hw, ctl->skb);
428 spin_lock(&wcn->dxe_lock);
429 if (WARN_ON(wcn->tx_ack_skb))
430 ieee80211_free_txskb(wcn->hw, wcn->tx_ack_skb);
431 wcn->tx_ack_skb = ctl->skb; /* Tracking ref */
432 mod_timer(&wcn->tx_ack_timer, jiffies + HZ / 10);
433 spin_unlock(&wcn->dxe_lock);
437 ieee80211_free_txskb(wcn->hw, ctl->skb);
440 if (wcn->queues_stopped) {
441 wcn->queues_stopped = false;
442 ieee80211_wake_queues(wcn->hw);
456 struct wcn36xx *wcn = (struct wcn36xx *)dev;
459 wcn36xx_dxe_read_register(wcn, WCN36XX_DXE_INT_SRC_RAW_REG, &int_src);
462 wcn36xx_dxe_read_register(wcn,
466 wcn36xx_dxe_write_register(wcn,
471 wcn36xx_dxe_write_register(wcn,
480 wcn36xx_dxe_write_register(wcn,
486 wcn36xx_dxe_write_register(wcn,
496 reap_tx_dxes(wcn, &wcn->dxe_tx_h_ch);
501 wcn36xx_dxe_read_register(wcn,
505 wcn36xx_dxe_write_register(wcn,
510 wcn36xx_dxe_write_register(wcn,
519 wcn36xx_dxe_write_register(wcn,
525 wcn36xx_dxe_write_register(wcn,
535 reap_tx_dxes(wcn, &wcn->dxe_tx_l_ch);
544 struct wcn36xx *wcn = (struct wcn36xx *)dev;
546 wcn36xx_dxe_rx_frame(wcn);
551 static int wcn36xx_dxe_request_irqs(struct wcn36xx *wcn)
555 ret = request_irq(wcn->tx_irq, wcn36xx_irq_tx_complete,
556 IRQF_TRIGGER_HIGH, "wcn36xx_tx", wcn);
562 ret = request_irq(wcn->rx_irq, wcn36xx_irq_rx_ready, IRQF_TRIGGER_HIGH,
563 "wcn36xx_rx", wcn);
569 enable_irq_wake(wcn->rx_irq);
574 free_irq(wcn->tx_irq, wcn);
580 static int wcn36xx_rx_handle_packets(struct wcn36xx *wcn,
594 wcn36xx_dxe_read_register(wcn, status_reg, &int_reason);
595 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_0_INT_CLR, int_mask);
598 wcn36xx_dxe_write_register(wcn,
606 wcn36xx_dxe_write_register(wcn,
611 wcn36xx_dxe_write_register(wcn,
631 ret = wcn36xx_dxe_fill_skb(wcn->dev, ctl, GFP_ATOMIC);
636 dma_unmap_single(wcn->dev, dma_addr, WCN36XX_PKT_SIZE,
638 wcn36xx_rx_skb(wcn, skb);
651 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_ENCH_ADDR, en_mask);
660 void wcn36xx_dxe_rx_frame(struct wcn36xx *wcn)
664 wcn36xx_dxe_read_register(wcn, WCN36XX_DXE_INT_SRC_RAW_REG, &int_src);
668 wcn36xx_rx_handle_packets(wcn, &wcn->dxe_rx_l_ch,
676 wcn36xx_rx_handle_packets(wcn, &wcn->dxe_rx_h_ch,
686 int wcn36xx_dxe_allocate_mem_pools(struct wcn36xx *wcn)
694 wcn->mgmt_mem_pool.chunk_size = WCN36XX_BD_CHUNK_SIZE +
697 s = wcn->mgmt_mem_pool.chunk_size * WCN36XX_DXE_CH_DESC_NUMB_TX_H;
698 cpu_addr = dma_alloc_coherent(wcn->dev, s,
699 &wcn->mgmt_mem_pool.phy_addr,
704 wcn->mgmt_mem_pool.virt_addr = cpu_addr;
709 wcn->data_mem_pool.chunk_size = WCN36XX_BD_CHUNK_SIZE +
712 s = wcn->data_mem_pool.chunk_size * WCN36XX_DXE_CH_DESC_NUMB_TX_L;
713 cpu_addr = dma_alloc_coherent(wcn->dev, s,
714 &wcn->data_mem_pool.phy_addr,
719 wcn->data_mem_pool.virt_addr = cpu_addr;
724 wcn36xx_dxe_free_mem_pools(wcn);
729 void wcn36xx_dxe_free_mem_pools(struct wcn36xx *wcn)
731 if (wcn->mgmt_mem_pool.virt_addr)
732 dma_free_coherent(wcn->dev, wcn->mgmt_mem_pool.chunk_size *
734 wcn->mgmt_mem_pool.virt_addr,
735 wcn->mgmt_mem_pool.phy_addr);
737 if (wcn->data_mem_pool.virt_addr) {
738 dma_free_coherent(wcn->dev, wcn->data_mem_pool.chunk_size *
740 wcn->data_mem_pool.virt_addr,
741 wcn->data_mem_pool.phy_addr);
745 int wcn36xx_dxe_tx_frame(struct wcn36xx *wcn,
757 ch = is_low ? &wcn->dxe_tx_l_ch : &wcn->dxe_tx_h_ch;
769 ieee80211_stop_queues(wcn->hw);
770 wcn->queues_stopped = true;
802 desc_skb->src_addr_l = dma_map_single(wcn->dev,
806 if (dma_mapping_error(wcn->dev, desc_skb->src_addr_l)) {
807 dev_err(wcn->dev, "unable to DMA map src_addr_l\n");
836 qcom_smem_state_update_bits(wcn->tx_rings_empty_state,
843 wcn36xx_dxe_write_register(wcn,
881 int wcn36xx_dxe_tx_flush(struct wcn36xx *wcn)
887 if (_wcn36xx_dxe_tx_channel_is_empty(&wcn->dxe_tx_l_ch) &&
888 _wcn36xx_dxe_tx_channel_is_empty(&wcn->dxe_tx_h_ch)) {
900 int wcn36xx_dxe_init(struct wcn36xx *wcn)
905 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_REG_CSR_RESET, reg_data);
910 if (wcn->is_pronto)
911 wcn36xx_ccu_write_register(wcn, WCN36XX_CCU_DXE_INT_SELECT_PRONTO, reg_data);
913 wcn36xx_ccu_write_register(wcn, WCN36XX_CCU_DXE_INT_SELECT_RIVA, reg_data);
918 ret = wcn36xx_dxe_init_descs(wcn, &wcn->dxe_tx_l_ch);
920 dev_err(wcn->dev, "Error allocating descriptor\n");
923 wcn36xx_dxe_init_tx_bd(&wcn->dxe_tx_l_ch, &wcn->data_mem_pool);
926 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_L,
927 wcn->dxe_tx_l_ch.head_blk_ctl->desc_phy_addr);
930 wcn36xx_dxe_write_register(wcn,
932 WCN36XX_DXE_WQ_TX_L(wcn));
934 wcn36xx_dxe_read_register(wcn, WCN36XX_DXE_REG_CH_EN, ®_data);
939 ret = wcn36xx_dxe_init_descs(wcn, &wcn->dxe_tx_h_ch);
941 dev_err(wcn->dev, "Error allocating descriptor\n");
945 wcn36xx_dxe_init_tx_bd(&wcn->dxe_tx_h_ch, &wcn->mgmt_mem_pool);
948 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_H,
949 wcn->dxe_tx_h_ch.head_blk_ctl->desc_phy_addr);
952 wcn36xx_dxe_write_register(wcn,
954 WCN36XX_DXE_WQ_TX_H(wcn));
956 wcn36xx_dxe_read_register(wcn, WCN36XX_DXE_REG_CH_EN, ®_data);
961 ret = wcn36xx_dxe_init_descs(wcn, &wcn->dxe_rx_l_ch);
963 dev_err(wcn->dev, "Error allocating descriptor\n");
968 wcn36xx_dxe_ch_alloc_skb(wcn, &wcn->dxe_rx_l_ch);
971 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_L,
972 wcn->dxe_rx_l_ch.head_blk_ctl->desc_phy_addr);
975 wcn36xx_dxe_write_register(wcn,
980 wcn36xx_dxe_write_register(wcn,
982 wcn->dxe_rx_l_ch.head_blk_ctl->desc->phy_next_l);
985 wcn36xx_dxe_write_register(wcn,
992 ret = wcn36xx_dxe_init_descs(wcn, &wcn->dxe_rx_h_ch);
994 dev_err(wcn->dev, "Error allocating descriptor\n");
999 wcn36xx_dxe_ch_alloc_skb(wcn, &wcn->dxe_rx_h_ch);
1002 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_H,
1003 wcn->dxe_rx_h_ch.head_blk_ctl->desc_phy_addr);
1006 wcn36xx_dxe_write_register(wcn,
1011 wcn36xx_dxe_write_register(wcn,
1013 wcn->dxe_rx_h_ch.head_blk_ctl->desc->phy_next_l);
1016 wcn36xx_dxe_write_register(wcn,
1020 ret = wcn36xx_dxe_request_irqs(wcn);
1024 timer_setup(&wcn->tx_ack_timer, wcn36xx_dxe_tx_timer, 0);
1027 wcn36xx_dxe_enable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_TX_L);
1028 wcn36xx_dxe_enable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_TX_H);
1029 wcn36xx_dxe_enable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_RX_L);
1030 wcn36xx_dxe_enable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_RX_H);
1035 wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_rx_h_ch);
1037 wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_rx_l_ch);
1039 wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_tx_h_ch);
1041 wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_tx_l_ch);
1046 void wcn36xx_dxe_deinit(struct wcn36xx *wcn)
1051 wcn36xx_dxe_disable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_RX_H);
1052 wcn36xx_dxe_disable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_RX_L);
1053 wcn36xx_dxe_disable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_TX_H);
1054 wcn36xx_dxe_disable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_TX_L);
1056 free_irq(wcn->tx_irq, wcn);
1057 free_irq(wcn->rx_irq, wcn);
1058 del_timer(&wcn->tx_ack_timer);
1060 if (wcn->tx_ack_skb) {
1061 ieee80211_tx_status_irqsafe(wcn->hw, wcn->tx_ack_skb);
1062 wcn->tx_ack_skb = NULL;
1067 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_REG_CSR_RESET, reg_data);
1069 wcn36xx_dxe_ch_free_skbs(wcn, &wcn->dxe_rx_l_ch);
1070 wcn36xx_dxe_ch_free_skbs(wcn, &wcn->dxe_rx_h_ch);
1072 wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_tx_l_ch);
1073 wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_tx_h_ch);
1074 wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_rx_l_ch);
1075 wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_rx_h_ch);