Lines Matching refs:set
604 * Read back AR_WA(ah) into a permanent copy and set bits 14 and 17.
1200 * set AHB_MODE not to do cacheline prefetches
1246 * So set the usable tx buf size also to half to
1269 u32 set = AR_STA_ID1_KSRCH_MODE;
1275 set |= AR_STA_ID1_ADHOC;
1283 set |= AR_STA_ID1_STA_AP;
1290 set = 0;
1293 REG_RMW(ah, AR_STA_ID1, set, mask);
1588 ath_err(common, "Failed to set channel\n");
2080 /* set HW specific DFS configuration */
2135 * frames. If request, set power mode of chip to
2725 /* BSP should set the corresponding MUX register correctly.
3056 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
3058 if (set)